Research of Low Inductance Loop Design in GaN HEMT Application

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Abstract

High electron mobility transistor (HEMT) is one popular research topic in the field of power electronic devices. Gallium Nitride (GaN) HEMT has the advantages of high slew rate and low operation loss. In high frequency application, parasitic impedance introduced from PCB layout can have huge impact on operation efficiency and reliability. Minimizing the loop inductance is important. In this paper, three different low inductance loop design methods are analyzed and compared in details. Numeral comparison based on finite elements analysis (FEA) is carried out. Double pulse test is carried to verify the idea. Simulation and experimental results of switching transient are given for comparison. Low inductance loop design is further corroborated by the switching loss and switching time characterization.
Original languageEnglish
Title of host publicationProceedings of the 44th Annual Conference of the IEEE Industrial Electronics Society
Number of pages5
PublisherIEEE
Publication date2018
DOIs
Publication statusPublished - 2018
Event44th Annual Conference of the IEEE Industrial Electronics Society - Omni Shoreham Hotel, Washington D.C., United States
Duration: 21 Oct 201823 Oct 2018
http://www.iecon2018.org/

Conference

Conference44th Annual Conference of the IEEE Industrial Electronics Society
LocationOmni Shoreham Hotel
CountryUnited States
CityWashington D.C.
Period21/10/201823/10/2018
Internet address

Keywords

  • GaN HEMT
  • Low inductance loop design
  • Parasitic extraction
  • Switching characterization

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