Research of Low Inductance Loop Design in GaN HEMT Application

Bainan Sun; Zhe Zhang; Michael A. E. Andersen

doi:10.1109/IECON.2018.8591732

Research of Low Inductance Loop Design in GaN HEMT Application

Bainan Sun, Zhe Zhang, Michael A. E. Andersen

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

High electron mobility transistor (HEMT) is one popular research topic in the field of power electronic devices. Gallium Nitride (GaN) HEMT has the advantages of high slew rate and low operation loss. In high frequency application, parasitic impedance introduced from PCB layout can have huge impact on operation efficiency and reliability. Minimizing the loop inductance is important. In this paper, three different low inductance loop design methods are analyzed and compared in details. Numeral comparison based on finite elements analysis (FEA) is carried out. Double pulse test is carried to verify the idea. Simulation and experimental results of switching transient are given for comparison. Low inductance loop design is further corroborated by the switching loss and switching time characterization.

Original language	English
Title of host publication	Proceedings of the 44th Annual Conference of the IEEE Industrial Electronics Society
Number of pages	5
Publisher	IEEE
Publication date	2018
DOIs	https://doi.org/10.1109/IECON.2018.8591732
Publication status	Published - 2018
Event	44th Annual Conference of the IEEE Industrial Electronics Society - Omni Shoreham Hotel, Washington D.C., United States Duration: 21 Oct 2018 → 23 Oct 2018 http://www.iecon2018.org/

Conference

Conference	44th Annual Conference of the IEEE Industrial Electronics Society
Location	Omni Shoreham Hotel
Country	United States
City	Washington D.C.
Period	21/10/2018 → 23/10/2018
Internet address	http://www.iecon2018.org/

Keywords

GaN HEMT
Low inductance loop design
Parasitic extraction
Switching characterization

Access to Document

10.1109/IECON.2018.8591732

IECON 2018Accepted author manuscript, 1.3 MB

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Cite this

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title = "Research of Low Inductance Loop Design in GaN HEMT Application",

abstract = "High electron mobility transistor (HEMT) is one popular research topic in the field of power electronic devices. Gallium Nitride (GaN) HEMT has the advantages of high slew rate and low operation loss. In high frequency application, parasitic impedance introduced from PCB layout can have huge impact on operation efficiency and reliability. Minimizing the loop inductance is important. In this paper, three different low inductance loop design methods are analyzed and compared in details. Numeral comparison based on finite elements analysis (FEA) is carried out. Double pulse test is carried to verify the idea. Simulation and experimental results of switching transient are given for comparison. Low inductance loop design is further corroborated by the switching loss and switching time characterization. ",

keywords = "GaN HEMT, Low inductance loop design, Parasitic extraction, Switching characterization",

author = "Bainan Sun and Zhe Zhang and Andersen, {Michael A. E.}",

year = "2018",

doi = "10.1109/IECON.2018.8591732",

language = "English",

booktitle = "Proceedings of the 44th Annual Conference of the IEEE Industrial Electronics Society",

publisher = "IEEE",

address = "United States",

note = "44th Annual Conference of the IEEE Industrial Electronics Society, IECON 2018 ; Conference date: 21-10-2018 Through 23-10-2018",

url = "http://www.iecon2018.org/",

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TY - GEN

T1 - Research of Low Inductance Loop Design in GaN HEMT Application

AU - Sun, Bainan

AU - Zhang, Zhe

AU - Andersen, Michael A. E.

PY - 2018

Y1 - 2018

N2 - High electron mobility transistor (HEMT) is one popular research topic in the field of power electronic devices. Gallium Nitride (GaN) HEMT has the advantages of high slew rate and low operation loss. In high frequency application, parasitic impedance introduced from PCB layout can have huge impact on operation efficiency and reliability. Minimizing the loop inductance is important. In this paper, three different low inductance loop design methods are analyzed and compared in details. Numeral comparison based on finite elements analysis (FEA) is carried out. Double pulse test is carried to verify the idea. Simulation and experimental results of switching transient are given for comparison. Low inductance loop design is further corroborated by the switching loss and switching time characterization.

AB - High electron mobility transistor (HEMT) is one popular research topic in the field of power electronic devices. Gallium Nitride (GaN) HEMT has the advantages of high slew rate and low operation loss. In high frequency application, parasitic impedance introduced from PCB layout can have huge impact on operation efficiency and reliability. Minimizing the loop inductance is important. In this paper, three different low inductance loop design methods are analyzed and compared in details. Numeral comparison based on finite elements analysis (FEA) is carried out. Double pulse test is carried to verify the idea. Simulation and experimental results of switching transient are given for comparison. Low inductance loop design is further corroborated by the switching loss and switching time characterization.

KW - GaN HEMT

KW - Low inductance loop design

KW - Parasitic extraction

KW - Switching characterization

U2 - 10.1109/IECON.2018.8591732

DO - 10.1109/IECON.2018.8591732

M3 - Article in proceedings

BT - Proceedings of the 44th Annual Conference of the IEEE Industrial Electronics Society

PB - IEEE

T2 - 44th Annual Conference of the IEEE Industrial Electronics Society

Y2 - 21 October 2018 through 23 October 2018

ER -