Abstract
High electron mobility transistor (HEMT) is one popular research topic in the field of power electronic devices. Gallium Nitride (GaN) HEMT has the advantages of high slew rate and low operation loss. In high frequency application, parasitic impedance introduced from PCB layout can have huge impact on operation efficiency and reliability. Minimizing the loop inductance is important. In this paper, three different low inductance loop design methods are analyzed and compared in details. Numeral comparison based on finite elements analysis (FEA) is carried out. Double pulse test is carried to verify the idea. Simulation and experimental results of switching transient are given for comparison. Low inductance loop design is further corroborated by the switching loss and switching time characterization.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 44th Annual Conference of the IEEE Industrial Electronics Society |
| Number of pages | 5 |
| Publisher | IEEE |
| Publication date | 2018 |
| DOIs | |
| Publication status | Published - 2018 |
| Event | 44th Annual Conference of the IEEE Industrial Electronics Society - Omni Shoreham Hotel, Washington D.C., United States Duration: 21 Oct 2018 → 23 Oct 2018 Conference number: 44 https://ieeexplore.ieee.org/xpl/conhome/8560606/proceeding |
Conference
| Conference | 44th Annual Conference of the IEEE Industrial Electronics Society |
|---|---|
| Number | 44 |
| Location | Omni Shoreham Hotel |
| Country/Territory | United States |
| City | Washington D.C. |
| Period | 21/10/2018 → 23/10/2018 |
| Internet address |
Keywords
- GaN HEMT
- Low inductance loop design
- Parasitic extraction
- Switching characterization