Abstract
This paper presents a Network-on-Chip (NoC) architecture that enables the network topology to be reconfigured. The architecture thus enables a generalized System-on-Chip (SoC) platform in which the topology can be customized for the application that is currently running on the chip, including long links and direct links between IP-blocks. The configurability is inserted as a layer between routers and links, and the architecture can therefore be used in combination with existing NoC routers, making it a general architecture. The topology is configured using energy-efficient topology switches based on physical circuit switching as found in FPGAs.
The paper presents the ReNoC (Reconfigurable NoC) architecture and evaluates its potential. The evaluation design shows a 56% decrease in power consumption compared to a static 2D mesh topology.
Original language | English |
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Title of host publication | Second ACM/IEEE International Symposium on Networks-on-Chip |
Editors | Kees Goossens, Davide Bertozzi |
Publisher | IEEE Computer Society Press |
Publication date | 2008 |
Pages | 55-64 |
ISBN (Print) | 0-7695-3098-2 |
DOIs | |
Publication status | Published - 2008 |
Event | Second ACM/IEEE International Symposium on Networks-on-Chip - Newcastle upon Tyne, United Kingdom Duration: 7 Apr 2008 → 10 Apr 2008 Conference number: 2 https://ieeexplore.ieee.org/xpl/conhome/4492707/proceeding |
Conference
Conference | Second ACM/IEEE International Symposium on Networks-on-Chip |
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Number | 2 |
Country/Territory | United Kingdom |
City | Newcastle upon Tyne |
Period | 07/04/2008 → 10/04/2008 |
Internet address |