ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology

Mikkel Bystrup Stensgaard, Jens Sparsø

    Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

    Abstract

    This paper presents a Network-on-Chip (NoC) architecture that enables the network topology to be reconfigured. The architecture thus enables a generalized System-on-Chip (SoC) platform in which the topology can be customized for the application that is currently running on the chip, including long links and direct links between IP-blocks. The configurability is inserted as a layer between routers and links, and the architecture can therefore be used in combination with existing NoC routers, making it a general architecture. The topology is configured using energy-efficient topology switches based on physical circuit switching as found in FPGAs. The paper presents the ReNoC (Reconfigurable NoC) architecture and evaluates its potential. The evaluation design shows a 56% decrease in power consumption compared to a static 2D mesh topology.
    Original languageEnglish
    Title of host publicationSecond ACM/IEEE International Symposium on Networks-on-Chip
    EditorsKees Goossens, Davide Bertozzi
    PublisherIEEE Computer Society Press
    Publication date2008
    Pages55-64
    ISBN (Print)0-7695-3098-2
    DOIs
    Publication statusPublished - 2008
    EventSecond ACM/IEEE International Symposium on Networks-on-Chip - Newcastle upon Tyne, United Kingdom
    Duration: 7 Apr 200810 Apr 2008
    Conference number: 2
    https://ieeexplore.ieee.org/xpl/conhome/4492707/proceeding

    Conference

    ConferenceSecond ACM/IEEE International Symposium on Networks-on-Chip
    Number2
    Country/TerritoryUnited Kingdom
    CityNewcastle upon Tyne
    Period07/04/200810/04/2008
    Internet address

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