ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology

Mikkel Bystrup Stensgaard; Jens Sparsø

doi:10.1109/NOCS.2008.4492725

ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology

Mikkel Bystrup Stensgaard, Jens Sparsø

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

Abstract

This paper presents a Network-on-Chip (NoC) architecture that enables the network topology to be reconfigured. The architecture thus enables a generalized System-on-Chip (SoC) platform in which the topology can be customized for the application that is currently running on the chip, including long links and direct links between IP-blocks. The configurability is inserted as a layer between routers and links, and the architecture can therefore be used in combination with existing NoC routers, making it a general architecture. The topology is configured using energy-efficient topology switches based on physical circuit switching as found in FPGAs. The paper presents the ReNoC (Reconfigurable NoC) architecture and evaluates its potential. The evaluation design shows a 56% decrease in power consumption compared to a static 2D mesh topology.

Original language	English
Title of host publication	Second ACM/IEEE International Symposium on Networks-on-Chip
Editors	Kees Goossens, Davide Bertozzi
Publisher	IEEE Computer Society Press
Publication date	2008
Pages	55-64
ISBN (Print)	0-7695-3098-2
DOIs	https://doi.org/10.1109/NOCS.2008.4492725
Publication status	Published - 2008
Event	Second ACM/IEEE International Symposium on Networks-on-Chip - Newcastle upon Tyne, United Kingdom Duration: 7 Apr 2008 → 10 Apr 2008 Conference number: 2 https://ieeexplore.ieee.org/xpl/conhome/4492707/proceeding

Conference

Conference	Second ACM/IEEE International Symposium on Networks-on-Chip
Number	2
Country/Territory	United Kingdom
City	Newcastle upon Tyne
Period	07/04/2008 → 10/04/2008
Internet address	https://ieeexplore.ieee.org/xpl/conhome/4492707/proceeding

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10.1109/NOCS.2008.4492725

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@inproceedings{1eca1277a3d64800b786deecb695da1b,

title = "ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology",

abstract = "This paper presents a Network-on-Chip (NoC) architecture that enables the network topology to be reconfigured. The architecture thus enables a generalized System-on-Chip (SoC) platform in which the topology can be customized for the application that is currently running on the chip, including long links and direct links between IP-blocks. The configurability is inserted as a layer between routers and links, and the architecture can therefore be used in combination with existing NoC routers, making it a general architecture. The topology is configured using energy-efficient topology switches based on physical circuit switching as found in FPGAs. The paper presents the ReNoC (Reconfigurable NoC) architecture and evaluates its potential. The evaluation design shows a 56\% decrease in power consumption compared to a static 2D mesh topology.",

author = "Stensgaard, \{Mikkel Bystrup\} and Jens Spars{\o}",

year = "2008",

doi = "10.1109/NOCS.2008.4492725",

language = "English",

isbn = "0-7695-3098-2",

pages = "55--64",

editor = "Kees Goossens and Davide Bertozzi",

booktitle = "Second ACM/IEEE International Symposium on Networks-on-Chip",

publisher = "IEEE Computer Society Press",

note = "Second ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2008 ; Conference date: 07-04-2008 Through 10-04-2008",

url = "https://ieeexplore.ieee.org/xpl/conhome/4492707/proceeding",

}

Stensgaard, MB & Sparsø, J 2008, ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology. in K Goossens & D Bertozzi (eds), Second ACM/IEEE International Symposium on Networks-on-Chip. IEEE Computer Society Press, pp. 55-64, Second ACM/IEEE International Symposium on Networks-on-Chip, Newcastle upon Tyne, United Kingdom, 07/04/2008. https://doi.org/10.1109/NOCS.2008.4492725

ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology. / Stensgaard, Mikkel Bystrup; Sparsø, Jens.
Second ACM/IEEE International Symposium on Networks-on-Chip. ed. / Kees Goossens; Davide Bertozzi. IEEE Computer Society Press, 2008. p. 55-64.

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

TY - GEN

T1 - ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology

AU - Stensgaard, Mikkel Bystrup

AU - Sparsø, Jens

N1 - Conference code: 2

PY - 2008

Y1 - 2008

N2 - This paper presents a Network-on-Chip (NoC) architecture that enables the network topology to be reconfigured. The architecture thus enables a generalized System-on-Chip (SoC) platform in which the topology can be customized for the application that is currently running on the chip, including long links and direct links between IP-blocks. The configurability is inserted as a layer between routers and links, and the architecture can therefore be used in combination with existing NoC routers, making it a general architecture. The topology is configured using energy-efficient topology switches based on physical circuit switching as found in FPGAs. The paper presents the ReNoC (Reconfigurable NoC) architecture and evaluates its potential. The evaluation design shows a 56% decrease in power consumption compared to a static 2D mesh topology.

AB - This paper presents a Network-on-Chip (NoC) architecture that enables the network topology to be reconfigured. The architecture thus enables a generalized System-on-Chip (SoC) platform in which the topology can be customized for the application that is currently running on the chip, including long links and direct links between IP-blocks. The configurability is inserted as a layer between routers and links, and the architecture can therefore be used in combination with existing NoC routers, making it a general architecture. The topology is configured using energy-efficient topology switches based on physical circuit switching as found in FPGAs. The paper presents the ReNoC (Reconfigurable NoC) architecture and evaluates its potential. The evaluation design shows a 56% decrease in power consumption compared to a static 2D mesh topology.

U2 - 10.1109/NOCS.2008.4492725

DO - 10.1109/NOCS.2008.4492725

M3 - Article in proceedings

SN - 0-7695-3098-2

SP - 55

EP - 64

BT - Second ACM/IEEE International Symposium on Networks-on-Chip

A2 - Goossens, Kees

A2 - Bertozzi, Davide

PB - IEEE Computer Society Press

T2 - Second ACM/IEEE International Symposium on Networks-on-Chip

Y2 - 7 April 2008 through 10 April 2008

ER -

ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology

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