This paper presents a modified architecture for an input queued switch that reduces external speedup. Maximal size scheduling algorithms for input-buffered crossbars requires a speedup between port card and switch card. The speedup is typically in the range of 2, to compensate for the scheduler performance degradation. This implies, that the required bandwidth between port card and switch card is 2 times the actual port speed, adding to cost and complexity. To reduce this bandwidth, a modified architecture is proposed that introduces a small amount of input and output memory on the switch card chip. This architecture allows for internal speedup in the switch card and the external speedup between port card and switch card can be reduced significantly. A simulation study is used for buffer dimensioning and demonstrates the feasibility of the proposed architecture.
|Title of host publication||Workshop on High Performance Switching and Routing, 2005. HPSR.|
|Publication status||Published - 2005|
|Event||Workshop on High Performance Switching and Routing - Hong Kong, China|
Duration: 12 May 2005 → 14 May 2005
|Workshop||Workshop on High Performance Switching and Routing|
|Period||12/05/2005 → 14/05/2005|