Reducing external speedup requirements for input-queued crossbars

Michael Stubert Berger

doi:10.1109/HPSR.2005.1503227

Reducing external speedup requirements for input-queued crossbars

Michael Stubert Berger

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research

309 Downloads (Pure)

Abstract

This paper presents a modified architecture for an input queued switch that reduces external speedup. Maximal size scheduling algorithms for input-buffered crossbars requires a speedup between port card and switch card. The speedup is typically in the range of 2, to compensate for the scheduler performance degradation. This implies, that the required bandwidth between port card and switch card is 2 times the actual port speed, adding to cost and complexity. To reduce this bandwidth, a modified architecture is proposed that introduces a small amount of input and output memory on the switch card chip. This architecture allows for internal speedup in the switch card and the external speedup between port card and switch card can be reduced significantly. A simulation study is used for buffer dimensioning and demonstrates the feasibility of the proposed architecture.

Original language	English
Title of host publication	Workshop on High Performance Switching and Routing, 2005. HPSR.
Publisher	IEEE
Publication date	2005
ISBN (Print)	0-7803-8924-7
DOIs	https://doi.org/10.1109/HPSR.2005.1503227
Publication status	Published - 2005
Event	Workshop on High Performance Switching and Routing - Hong Kong, China Duration: 12 May 2005 → 14 May 2005 http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=10052

Workshop

Workshop	Workshop on High Performance Switching and Routing
Country/Territory	China
City	Hong Kong
Period	12/05/2005 → 14/05/2005
Internet address	http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=10052

Bibliographical note

Copyright: 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

Access to Document

10.1109/HPSR.2005.1503227

BergerFinal published version, 814 KB

OpenUrl availability

Full text

Cite this

@inproceedings{3dc6450000454ff09344afdb4c63318d,

title = "Reducing external speedup requirements for input-queued crossbars",

abstract = "This paper presents a modified architecture for an input queued switch that reduces external speedup. Maximal size scheduling algorithms for input-buffered crossbars requires a speedup between port card and switch card. The speedup is typically in the range of 2, to compensate for the scheduler performance degradation. This implies, that the required bandwidth between port card and switch card is 2 times the actual port speed, adding to cost and complexity. To reduce this bandwidth, a modified architecture is proposed that introduces a small amount of input and output memory on the switch card chip. This architecture allows for internal speedup in the switch card and the external speedup between port card and switch card can be reduced significantly. A simulation study is used for buffer dimensioning and demonstrates the feasibility of the proposed architecture.",

author = "Berger, {Michael Stubert}",

note = "Copyright: 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE; Workshop on High Performance Switching and Routing, HPSR'05 ; Conference date: 12-05-2005 Through 14-05-2005",

year = "2005",

doi = "10.1109/HPSR.2005.1503227",

language = "English",

isbn = "0-7803-8924-7",

booktitle = "Workshop on High Performance Switching and Routing, 2005. HPSR.",

publisher = "IEEE",

address = "United States",

url = "http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=10052",

}

TY - GEN

T1 - Reducing external speedup requirements for input-queued crossbars

AU - Berger, Michael Stubert

N1 - Copyright: 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

PY - 2005

Y1 - 2005

N2 - This paper presents a modified architecture for an input queued switch that reduces external speedup. Maximal size scheduling algorithms for input-buffered crossbars requires a speedup between port card and switch card. The speedup is typically in the range of 2, to compensate for the scheduler performance degradation. This implies, that the required bandwidth between port card and switch card is 2 times the actual port speed, adding to cost and complexity. To reduce this bandwidth, a modified architecture is proposed that introduces a small amount of input and output memory on the switch card chip. This architecture allows for internal speedup in the switch card and the external speedup between port card and switch card can be reduced significantly. A simulation study is used for buffer dimensioning and demonstrates the feasibility of the proposed architecture.

AB - This paper presents a modified architecture for an input queued switch that reduces external speedup. Maximal size scheduling algorithms for input-buffered crossbars requires a speedup between port card and switch card. The speedup is typically in the range of 2, to compensate for the scheduler performance degradation. This implies, that the required bandwidth between port card and switch card is 2 times the actual port speed, adding to cost and complexity. To reduce this bandwidth, a modified architecture is proposed that introduces a small amount of input and output memory on the switch card chip. This architecture allows for internal speedup in the switch card and the external speedup between port card and switch card can be reduced significantly. A simulation study is used for buffer dimensioning and demonstrates the feasibility of the proposed architecture.

U2 - 10.1109/HPSR.2005.1503227

DO - 10.1109/HPSR.2005.1503227

M3 - Article in proceedings

SN - 0-7803-8924-7

BT - Workshop on High Performance Switching and Routing, 2005. HPSR.

PB - IEEE

T2 - Workshop on High Performance Switching and Routing

Y2 - 12 May 2005 through 14 May 2005

ER -

Reducing external speedup requirements for input-queued crossbars

Abstract

Workshop

Bibliographical note

Access to Document

OpenUrl availability

Fingerprint

Cite this