Reducing external speedup requirements for input-queued crossbars

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Abstract

This paper presents a modified architecture for an input queued switch that reduces external speedup. Maximal size scheduling algorithms for input-buffered crossbars requires a speedup between port card and switch card. The speedup is typically in the range of 2, to compensate for the scheduler performance degradation. This implies, that the required bandwidth between port card and switch card is 2 times the actual port speed, adding to cost and complexity. To reduce this bandwidth, a modified architecture is proposed that introduces a small amount of input and output memory on the switch card chip. This architecture allows for internal speedup in the switch card and the external speedup between port card and switch card can be reduced significantly. A simulation study is used for buffer dimensioning and demonstrates the feasibility of the proposed architecture.
Original languageEnglish
Title of host publicationWorkshop on High Performance Switching and Routing, 2005. HPSR.
PublisherIEEE
Publication date2005
ISBN (Print)0-7803-8924-7
DOIs
Publication statusPublished - 2005
EventWorkshop on High Performance Switching and Routing - Hong Kong, China
Duration: 12 May 200514 May 2005
http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=10052

Workshop

WorkshopWorkshop on High Performance Switching and Routing
CountryChina
CityHong Kong
Period12/05/200514/05/2005
Internet address

Bibliographical note

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