Reconﬁgurable computing allows application programmers to signiﬁcantly increase the speed of software algorithms by implementing computationally demanding tasks in hardware while maintaining a certain degree of ﬂexibility. This can be achieved by using FPGAs to implement hardware accelerators that can be reconﬁgured when no longer needed, enabling the re-use of the resources of the FPGAs to realise new functionalities. For multi-core platforms, reconﬁguration can be extended to the infrastructure supporting intercorecommunication and used to dynamically modify the characteristics of the communication channels between the tasks that are aﬀected by the reconﬁguration. This thesis investigates the use of reconﬁguration in the context of multicore realtime systems targeting embedded applications. We address the reconﬁguration of both the computation and the communication resources of a multi-core platform. Our approach is to associate reconﬁguration with operational mode changes where the system, during normal operation, changes a subset of the executing tasks to adapt its behaviour to new conditions. Reconﬁguration is therefore used during a mode change to modify the real-time guaranteed services provided by the hardware platform to ﬁt the requirements of the current mode.
The reconﬁguration of the computation resources consists of altering the hardware implementation of selected resources, such as accelerators, and it is achieved by using the dynamic partial reconﬁguration feature oﬀered by FPGAs. With regards to this, we also present a lightweight reconﬁguration controller, named RT-ICAP,specially developed to supporttime predictable dynamic partial reconﬁguration. There conﬁguration of the communication resources consists of setting up and tearing down the end-to-end channels oﬀered by the communication fabric between the cores of the platform. To support this, we present a new network on chip architecture, named Argo 2, that allows instantaneous and time-predictable reconﬁguration of the communication channels. Our reconﬁguration-capable architecture is prototyped using the existing time-predictable multi-processor platform T-CREST. The thesis also presents low-level reconﬁguration time analysis for these architectures. The evaluation of the proposed approach and the developed architectures is carried out using synthetic benchmarks and hardware accelerators generated by high-level synthesis tools. For the reconﬁguration of computation resources, the results show that the use of accelerators in combination with dynamic partial reconﬁguration leads to better utilisation of the FPGA resources and tighter worst-case execution time bounds than a pure software solution. Moreover, the results show that using are conﬁgurable solution delivers a worst case performance comparable with that of a non-reconﬁgurable solution. For the reconﬁguration of communication resources, the results show that the worst-case reconﬁguration time ranges from hundreds to thousands of clock cycles, making our solution considerably faster than other functionally equivalent networks-on-chips. In addition to the evaluation based on synthetic benchmarks, we also present a proof-of-concept case study based on a multi-core audio digital signal-processing application that combines reconﬁguration of both the computation and communication resources. The case study shows that the presented approaches for reconﬁguration can be eﬀectively used in a real-world application and can lead to a reduction of the overall hardware size and better use of the platform resources while maintaining comparable computation performance with respect to a non-reconﬁgurable approach.
|Number of pages||152|
|Publication status||Published - 2018|
|Series||DTU Compute PHD-2018|