Abstract
This paper evaluates the applicability of transactional mem-
ory to the implementation of dierent non-blocking data
structures in the context of the Real-time Specication for
Java. In particular, we argue that hardware support for
micro-transaction allows us to implement eciently data
structures that are often dicult to realize with the atomic
operations provided by stock hardware. Our main imple-
mentation platform is the Java Optimized Processor sys-
tem. We report on the performance of data structures imple-
mented with locks, compare and swap and micro-transactions.
Our results conrm that transactional memory is an inter-
esting alternative to traditional concurrency control mecha-
nisms.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 9th International Workshop on Java Technologies for Real-Time and Embedded Systems (JTRES 2011) |
| Number of pages | 10 |
| Publisher | ACM |
| Publication date | 2011 |
| ISBN (Print) | 978-1-4503-0731-4 |
| DOIs | |
| Publication status | Published - 2011 |
| Event | 9th International Workshop on Java Technologies for Real-Time and Embedded Systems - York, United Kingdom Duration: 26 Sept 2011 → 28 Sept 2011 Conference number: 9 http://www.informatik.uni-trier.de/~ley/db/conf/jtres/jtres2011.html |
Workshop
| Workshop | 9th International Workshop on Java Technologies for Real-Time and Embedded Systems |
|---|---|
| Number | 9 |
| Country/Territory | United Kingdom |
| City | York |
| Period | 26/09/2011 → 28/09/2011 |
| Internet address |
Bibliographical note
© ACM, 2011. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in JTRES '11, http://doi.acm.org/10.1145/2043910.2043912Keywords
- Wait-Free queue
- MCAS
- CAS
- Transactional Memory