Radix-16 Combined Division and Square Root Unit

Alberto Nannarelli

doi:10.1109/ARITH.2011.30

Radix-16 Combined Division and Square Root Unit

Alberto Nannarelli

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

Abstract

Division and square root, based on the digitrecurrence algorithm, can be implemented in a combined unit. Several implementations of combined division/square root units have been presented mostly for radices 2 and 4. Here, we present a combined radix-16 unit obtained by overlapping two radix-4 result digit selection functions, as it is normally done for division only units. The latency of the unit is reduced by retiming and low power methods are applied as well. The proposed unit is compared to a radix-4 combined division/square root unit, and to a radix-16 unit, obtained by cascading two radix-4 stages, which is similar to the one implemented in a state-of-the-art processor.

Original language	English
Title of host publication	2011 20th IEEE Symposium on Computer Arithmetic (ARITH)
Publisher	IEEE
Publication date	2011
Pages	169-176
ISBN (Print)	978-1-4244-9457-6
DOIs	https://doi.org/10.1109/ARITH.2011.30
Publication status	Published - 2011
Event	20th IEEE Symposium on Computer Arithmetic - Tübingen, Germany Duration: 25 Jul 2011 → 27 Jul 2011 Conference number: 20 https://ieeexplore.ieee.org/xpl/conhome/5991607/proceeding

Conference

Conference	20th IEEE Symposium on Computer Arithmetic
Number	20
Country/Territory	Germany
City	Tübingen
Period	25/07/2011 → 27/07/2011
Internet address	https://ieeexplore.ieee.org/xpl/conhome/5991607/proceeding

Series	Proceedings of the Symposium on Computer Arithmetic
ISSN	1063-6889

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title = "Radix-16 Combined Division and Square Root Unit",

abstract = "Division and square root, based on the digitrecurrence algorithm, can be implemented in a combined unit. Several implementations of combined division/square root units have been presented mostly for radices 2 and 4. Here, we present a combined radix-16 unit obtained by overlapping two radix-4 result digit selection functions, as it is normally done for division only units. The latency of the unit is reduced by retiming and low power methods are applied as well. The proposed unit is compared to a radix-4 combined division/square root unit, and to a radix-16 unit, obtained by cascading two radix-4 stages, which is similar to the one implemented in a state-of-the-art processor.",

author = "Alberto Nannarelli",

year = "2011",

doi = "10.1109/ARITH.2011.30",

language = "English",

isbn = "978-1-4244-9457-6",

series = "Proceedings of the Symposium on Computer Arithmetic",

publisher = "IEEE",

pages = "169--176",

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address = "United States",

note = "20th IEEE Symposium on Computer Arithmetic, ARITH 2011 ; Conference date: 25-07-2011 Through 27-07-2011",

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N1 - Conference code: 20

PY - 2011

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N2 - Division and square root, based on the digitrecurrence algorithm, can be implemented in a combined unit. Several implementations of combined division/square root units have been presented mostly for radices 2 and 4. Here, we present a combined radix-16 unit obtained by overlapping two radix-4 result digit selection functions, as it is normally done for division only units. The latency of the unit is reduced by retiming and low power methods are applied as well. The proposed unit is compared to a radix-4 combined division/square root unit, and to a radix-16 unit, obtained by cascading two radix-4 stages, which is similar to the one implemented in a state-of-the-art processor.

AB - Division and square root, based on the digitrecurrence algorithm, can be implemented in a combined unit. Several implementations of combined division/square root units have been presented mostly for radices 2 and 4. Here, we present a combined radix-16 unit obtained by overlapping two radix-4 result digit selection functions, as it is normally done for division only units. The latency of the unit is reduced by retiming and low power methods are applied as well. The proposed unit is compared to a radix-4 combined division/square root unit, and to a radix-16 unit, obtained by cascading two radix-4 stages, which is similar to the one implemented in a state-of-the-art processor.

U2 - 10.1109/ARITH.2011.30

DO - 10.1109/ARITH.2011.30

M3 - Article in proceedings

SN - 978-1-4244-9457-6

T3 - Proceedings of the Symposium on Computer Arithmetic

SP - 169

EP - 176

BT - 2011 20th IEEE Symposium on Computer Arithmetic (ARITH)

PB - IEEE

T2 - 20th IEEE Symposium on Computer Arithmetic

Y2 - 25 July 2011 through 27 July 2011

ER -

Radix-16 Combined Division and Square Root Unit

Abstract

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