Radix-16 Combined Division and Square Root Unit

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    Abstract

    Division and square root, based on the digitrecurrence algorithm, can be implemented in a combined unit. Several implementations of combined division/square root units have been presented mostly for radices 2 and 4. Here, we present a combined radix-16 unit obtained by overlapping two radix-4 result digit selection functions, as it is normally done for division only units. The latency of the unit is reduced by retiming and low power methods are applied as well. The proposed unit is compared to a radix-4 combined division/square root unit, and to a radix-16 unit, obtained by cascading two radix-4 stages, which is similar to the one implemented in a state-of-the-art processor.
    Original languageEnglish
    Title of host publication2011 20th IEEE Symposium on Computer Arithmetic (ARITH)
    PublisherIEEE
    Publication date2011
    Pages169-176
    ISBN (Print)978-1-4244-9457-6
    DOIs
    Publication statusPublished - 2011
    EventIEEE Symposium on Computer Arithmetic - Montpellier, France
    Duration: 1 Jan 2011 → …
    Conference number: 20

    Conference

    ConferenceIEEE Symposium on Computer Arithmetic
    Number20
    CityMontpellier, France
    Period01/01/2011 → …
    SeriesProceedings of the Symposium on Computer Arithmetic
    ISSN1063-6889

    Cite this

    Nannarelli, A. (2011). Radix-16 Combined Division and Square Root Unit. In 2011 20th IEEE Symposium on Computer Arithmetic (ARITH) (pp. 169-176). IEEE. Proceedings of the Symposium on Computer Arithmetic https://doi.org/10.1109/ARITH.2011.30