Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems

Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alex Doboli, Paul Pop

    Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

    233 Downloads (Pure)


    The paper presents an approach to process scheduling for embedded systems. Target architectures consist of several processors and ASICs connected by shared busses. We have developed algorithms for process graph scheduling based on listscheduling and branch-and-bound strategies. One essential contribution is in the manner in which information on process allocation is used in order to efficiently derive a good quality or optimal schedule. Experiments show the superiority of these algorithms compared to previous approaches like critical-path heuristics and ILP based optimal scheduling. An extension of our approach allows the scheduling of conditional process graphs capturing both data and control flow. In this case a schedule table has to be generated so that the worst case delay is minimized.
    Original languageEnglish
    Title of host publicationEuromicro Conference, 1998. Proceedings. 24th
    Publication date1998
    ISBN (Print)0-8186-8646-4
    Publication statusPublished - 1998
    Event24 th. EUROMICRO Conference -
    Duration: 1 Jan 1998 → …
    Conference number: 24


    Conference24 th. EUROMICRO Conference
    Period01/01/1998 → …
    SeriesEuromicro Conference. Proceedings

    Fingerprint Dive into the research topics of 'Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems'. Together they form a unique fingerprint.

    Cite this