Abstract
With increased densities on chips and the growing popularity of multicore processors and general-purpose graphics processing units (GPGPUs) power dissipation and energy consumption pose a serious challenge in the design of system-on-chips (SoCs) and a rise in costs for heat removal. In this work, we analyze the impact of power dissipation in floating-point (FP) units and we consider different alternatives in the implementation of FP-division that lead to substantial energy savings. We compare the implementation of division in a Fused Multiply-Add (FMA) unit based on the Newton-Raphson approximation algorithm to the implementation in a dedicated digit-recurrence unit. The results show a significant reduction of energy in a typical scientific application when the division digit-recurrence unit is used. In addition, we model the thermal behavior of the considered FP-units.
| Original language | English |
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| Title of host publication | Proceedings of 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2010) |
| Publisher | IEEE |
| Publication date | 2010 |
| Pages | 257-264 |
| ISBN (Print) | 978-1-4244-6966-6 |
| DOIs | |
| Publication status | Published - 2010 |
| Event | 21st IEEE International Conference on Application-specific Systems, Architectures and Processors - Rennes, France Duration: 7 Jul 2010 → 9 Jul 2010 Conference number: 21 http://asap2010.inria.fr/ |
Conference
| Conference | 21st IEEE International Conference on Application-specific Systems, Architectures and Processors |
|---|---|
| Number | 21 |
| Country/Territory | France |
| City | Rennes |
| Period | 07/07/2010 → 09/07/2010 |
| Internet address |
