Power Constrained High-Level Synthesis of Battery Powered Digital Systems

Sune Fallgaard Nielsen, Jan Madsen

    Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

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    Abstract

    We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle constraints. Our approach eliminates the large power spikes, resulting in an increased battery lifetime, a property of utmost importance for battery powered embedded systems. Our approach extends the partial-clique partitioning algorithm by introducing power awareness through a heuristic algorithm which bounds the design space to those of power feasible schedules. We have applied our algorithm on a set of dataflow graphs and investigated the impact on circuit area when applying different power constraints.
    Original languageEnglish
    Title of host publicationDATE 2003
    PublisherIEEE
    Publication date2003
    Pages1136-1137
    ISBN (Print)0-7695-1870-2
    Publication statusPublished - 2003
    Event2003 Design, Automation and Test in Europe Conference and Exposition - Munich, Germany
    Duration: 3 Mar 20037 Mar 2003
    http://www.informatik.uni-trier.de/~ley/db/conf/date/date2003.html

    Conference

    Conference2003 Design, Automation and Test in Europe Conference and Exposition
    Country/TerritoryGermany
    CityMunich
    Period03/03/200307/03/2003
    Internet address

    Bibliographical note

    Copyright: 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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