Power Constrained High-Level Synthesis of Battery Powered Digital Systems

Sune Fallgaard Nielsen, Jan Madsen

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    We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle constraints. Our approach eliminates the large power spikes, resulting in an increased battery lifetime, a property of utmost importance for battery powered embedded systems. Our approach extends the partial-clique partitioning algorithm by introducing power awareness through a heuristic algorithm which bounds the design space to those of power feasible schedules. We have applied our algorithm on a set of dataflow graphs and investigated the impact on circuit area when applying different power constraints.
    Original languageEnglish
    Title of host publicationDATE 2003
    Publication date2003
    ISBN (Print)0-7695-1870-2
    Publication statusPublished - 2003
    Event2003 Design, Automation and Test in Europe Conference and Exposition - Munich, Germany
    Duration: 3 Mar 20037 Mar 2003


    Conference2003 Design, Automation and Test in Europe Conference and Exposition
    Internet address

    Bibliographical note

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