Power Constrained High-Level Synthesis of Battery Powered Digital Systems

Sune Fallgaard Nielsen; Jan Madsen

Power Constrained High-Level Synthesis of Battery Powered Digital Systems

Sune Fallgaard Nielsen, Jan Madsen

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Abstract

We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle constraints. Our approach eliminates the large power spikes, resulting in an increased battery lifetime, a property of utmost importance for battery powered embedded systems. Our approach extends the partial-clique partitioning algorithm by introducing power awareness through a heuristic algorithm which bounds the design space to those of power feasible schedules. We have applied our algorithm on a set of dataflow graphs and investigated the impact on circuit area when applying different power constraints.

Original language	English
Title of host publication	DATE 2003
Publisher	IEEE
Publication date	2003
Pages	1136-1137
ISBN (Print)	0-7695-1870-2
Publication status	Published - 2003
Event	2003 Design, Automation and Test in Europe Conference and Exposition - Munich, Germany Duration: 3 Mar 2003 → 7 Mar 2003 http://www.informatik.uni-trier.de/~ley/db/conf/date/date2003.html

Conference

Conference	2003 Design, Automation and Test in Europe Conference and Exposition
Country/Territory	Germany
City	Munich
Period	03/03/2003 → 07/03/2003
Internet address	http://www.informatik.uni-trier.de/~ley/db/conf/date/date2003.html

Bibliographical note

Copyright: 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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@inproceedings{5a06cad47ac34463937cafa275abf038,

title = "Power Constrained High-Level Synthesis of Battery Powered Digital Systems",

abstract = "We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle constraints. Our approach eliminates the large power spikes, resulting in an increased battery lifetime, a property of utmost importance for battery powered embedded systems. Our approach extends the partial-clique partitioning algorithm by introducing power awareness through a heuristic algorithm which bounds the design space to those of power feasible schedules. We have applied our algorithm on a set of dataflow graphs and investigated the impact on circuit area when applying different power constraints.",

author = "Nielsen, {Sune Fallgaard} and Jan Madsen",

note = "Copyright: 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE; 2003 Design, Automation and Test in Europe Conference and Exposition, DATE 2003 ; Conference date: 03-03-2003 Through 07-03-2003",

year = "2003",

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T1 - Power Constrained High-Level Synthesis of Battery Powered Digital Systems

AU - Nielsen, Sune Fallgaard

AU - Madsen, Jan

N1 - Copyright: 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

PY - 2003

Y1 - 2003

N2 - We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle constraints. Our approach eliminates the large power spikes, resulting in an increased battery lifetime, a property of utmost importance for battery powered embedded systems. Our approach extends the partial-clique partitioning algorithm by introducing power awareness through a heuristic algorithm which bounds the design space to those of power feasible schedules. We have applied our algorithm on a set of dataflow graphs and investigated the impact on circuit area when applying different power constraints.

AB - We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle constraints. Our approach eliminates the large power spikes, resulting in an increased battery lifetime, a property of utmost importance for battery powered embedded systems. Our approach extends the partial-clique partitioning algorithm by introducing power awareness through a heuristic algorithm which bounds the design space to those of power feasible schedules. We have applied our algorithm on a set of dataflow graphs and investigated the impact on circuit area when applying different power constraints.

M3 - Article in proceedings

SN - 0-7695-1870-2

SP - 1136

EP - 1137

BT - DATE 2003

PB - IEEE

T2 - 2003 Design, Automation and Test in Europe Conference and Exposition

Y2 - 3 March 2003 through 7 March 2003

ER -

Power Constrained High-Level Synthesis of Battery Powered Digital Systems

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