With technology scaled to deep submicron era, temperature and temperature gradient have emerged as important design criteria. We propose two post-placement techniques to reduce peak temperature by intelligently allocating whitespace in the hotspots. Both methods are fully compliant with commercial technologies, and can be easily integrated with state-of-the-art thermal-aware design flow. Experiments in a set of tests on circuits implemented in STM 65nm technologies show that our methods achieve better peak temperature reduction than directly increasing circuit's area.
|Title of host publication||Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010|
|Publication status||Published - 2010|
|Event||Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010 - |
Duration: 1 Jan 2010 → …
|Conference||Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010|
|Period||01/01/2010 → …|