Post-placement temperature reduction techniques

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    Abstract

    With technology scaled to deep submicron era, temperature and temperature gradient have emerged as important design criteria. We propose two post-placement techniques to reduce peak temperature by intelligently allocating whitespace in the hotspots. Both methods are fully compliant with commercial technologies, and can be easily integrated with state-of-the-art thermal-aware design flow. Experiments in a set of tests on circuits implemented in STM 65nm technologies show that our methods achieve better peak temperature reduction than directly increasing circuit's area.
    Original languageEnglish
    Title of host publicationDesign, Automation & Test in Europe Conference & Exhibition (DATE), 2010
    PublisherIEEE
    Publication date2010
    Pages634-637
    ISBN (Print)978-1-4244-7054-9
    Publication statusPublished - 2010
    EventDesign, Automation & Test in Europe Conference & Exhibition (DATE), 2010 -
    Duration: 1 Jan 2010 → …

    Conference

    ConferenceDesign, Automation & Test in Europe Conference & Exhibition (DATE), 2010
    Period01/01/2010 → …

    Bibliographical note

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