Patmos: a time-predictable microprocessor

Martin Schoeberl*, Wolfgang Puffitsch, Stefan Hepp, Benedikt Huber, Daniel Prokesch

*Corresponding author for this work

Research output: Contribution to journalJournal articleResearchpeer-review

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Abstract

Current processors provide high average-case performance, as they are optimized for general purpose computing. However, those optimizations often lead to a high worst-case execution time (WCET). WCET analysis tools model the architectural features that increase average-case performance. To keep analysis complexity manageable, those models need to abstract from implementation details. This abstraction further increases the WCET bound. This paper presents a way out of this dilemma: a processor designed for real-time systems. We design and optimize a processor, called Patmos, for low WCET bounds rather than for high average-case performance. Patmos is a dual-issue, statically scheduled RISC processor. A method cache serves as the cache for the instructions and a split cache organization simplifies the WCET analysis of the data cache. To fill the dual-issue pipeline with enough useful instructions, Patmos relies on a customized compiler. The compiler also plays a central role in optimizing the application for the WCET instead of average-case performance.
Original languageEnglish
JournalReal-Time Systems
Volume54
Issue number2
Pages (from-to)1-35
ISSN0922-6443
DOIs
Publication statusPublished - 2018

Keywords

  • Real-time systems
  • Time-predictable architecture
  • Worst-case execution time

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