Optimization of Nonlinear Figure-of-Merits of Integrated Power MOSFETs in Partial SOI Process

Lin Fan; Ivan Harald Holger Jørgensen; Arnold Knott

doi:10.1109/ET.2016.7753476

Optimization of Nonlinear Figure-of-Merits of Integrated Power MOSFETs in Partial SOI Process

Lin Fan, Ivan Harald Holger Jørgensen, Arnold Knott

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Abstract

State-of-the-art power semiconductor industry uses figure-of-merits (FOMs) for technology-to-technology and/or device-to-device comparisons. However, the existing FOMs are fundamentally nonlinear due to the nonlinearities of the parameters such as the gate charge and the output charge versus different operating conditions. A systematic analysis of the optimization of these FOMs has not been previously established. The optimization methods are verified on a 100 V power MOSFET implemented in a 0.18 µm partial SOI process. Its FOMs are lowered by 1.3-18.3 times and improved by 22-95 % with optimized conditions of quasi-zero voltage switching

Original language	English
Title of host publication	Proceedings of XXV International Scientific Conference Electronics
Number of pages	4
Publisher	IEEE
Publication date	2016
ISBN (Print)	978-1-5090-2883-2
DOIs	https://doi.org/10.1109/ET.2016.7753476
Publication status	Published - 2016
Event	XXV International Scientific Conference Electronics - Sozopol, Bulgaria Duration: 12 Sept 2016 → 14 Sept 2016

Conference

Conference	XXV International Scientific Conference Electronics
Country/Territory	Bulgaria
City	Sozopol
Period	12/09/2016 → 14/09/2016

Keywords

Figure of Merit
Gate Charge
Output Charge
Power MOSFET
Silicon-on-Insulator

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title = "Optimization of Nonlinear Figure-of-Merits of Integrated Power MOSFETs in Partial SOI Process",

abstract = "State-of-the-art power semiconductor industry uses figure-of-merits (FOMs) for technology-to-technology and/or device-to-device comparisons. However, the existing FOMs are fundamentally nonlinear due to the nonlinearities of the parameters such as the gate charge and the output charge versus different operating conditions. A systematic analysis of the optimization of these FOMs has not been previously established. The optimization methods are verified on a 100 V power MOSFET implemented in a 0.18 µm partial SOI process. Its FOMs are lowered by 1.3-18.3 times and improved by 22-95 % with optimized conditions of quasi-zero voltage switching",

keywords = "Figure of Merit, Gate Charge, Output Charge, Power MOSFET, Silicon-on-Insulator",

author = "Lin Fan and J{\o}rgensen, {Ivan Harald Holger} and Arnold Knott",

year = "2016",

doi = "10.1109/ET.2016.7753476",

language = "English",

isbn = "978-1-5090-2883-2",

booktitle = "Proceedings of XXV International Scientific Conference Electronics",

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address = "United States",

note = "XXV International Scientific Conference Electronics , ET2016 ; Conference date: 12-09-2016 Through 14-09-2016",

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AU - Fan, Lin

AU - Jørgensen, Ivan Harald Holger

AU - Knott, Arnold

PY - 2016

Y1 - 2016

N2 - State-of-the-art power semiconductor industry uses figure-of-merits (FOMs) for technology-to-technology and/or device-to-device comparisons. However, the existing FOMs are fundamentally nonlinear due to the nonlinearities of the parameters such as the gate charge and the output charge versus different operating conditions. A systematic analysis of the optimization of these FOMs has not been previously established. The optimization methods are verified on a 100 V power MOSFET implemented in a 0.18 µm partial SOI process. Its FOMs are lowered by 1.3-18.3 times and improved by 22-95 % with optimized conditions of quasi-zero voltage switching

AB - State-of-the-art power semiconductor industry uses figure-of-merits (FOMs) for technology-to-technology and/or device-to-device comparisons. However, the existing FOMs are fundamentally nonlinear due to the nonlinearities of the parameters such as the gate charge and the output charge versus different operating conditions. A systematic analysis of the optimization of these FOMs has not been previously established. The optimization methods are verified on a 100 V power MOSFET implemented in a 0.18 µm partial SOI process. Its FOMs are lowered by 1.3-18.3 times and improved by 22-95 % with optimized conditions of quasi-zero voltage switching

KW - Figure of Merit

KW - Gate Charge

KW - Output Charge

KW - Power MOSFET

KW - Silicon-on-Insulator

U2 - 10.1109/ET.2016.7753476

DO - 10.1109/ET.2016.7753476

M3 - Article in proceedings

SN - 978-1-5090-2883-2

BT - Proceedings of XXV International Scientific Conference Electronics

PB - IEEE

T2 - XXV International Scientific Conference Electronics

Y2 - 12 September 2016 through 14 September 2016

ER -

Optimization of Nonlinear Figure-of-Merits of Integrated Power MOSFETs in Partial SOI Process

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