Optimization of Modulator and Circuits for Low Power Continuous-Time Delta-Sigma ADC

Niels Marker-Villumsen; Erik Bruun

doi:10.1109/norchip.2014.7004723

Optimization of Modulator and Circuits for Low Power Continuous-Time Delta-Sigma ADC

Niels Marker-Villumsen, Erik Bruun

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Abstract

This paper presents a new optimization method for achieving a minimum current consumption in a continuous-time Delta-Sigma analog-to-digital converter (ADC). The method is applied to a continuous-time modulator realised with active-RC integrators and with a folded-cascode operational transconduc- tance amplifier (OTA). Based on a detailed circuit analysis of the integrator and the OTA, key expression are derived relating the biasing current of the OTA to the noise requirements of the integrator. In the optimization the corner frequency of the modulator loop filter and the number of quantizer levels are swept. Based on the results of the circuit analysis, for each modulator combination the summed current consumption of the 1st integrator and quantizer of the ADC is determined. By also sweeping the partitioning of the noise power for the different circuit parts, the optimum modulator and circuit solution that fulfils a predefined set of performance requirements at minimum current is found. A design example is provided for a 3rd order modulator, achieving for the OTA of the 1st integrator and the quantizer a summed current consumption of 28 A. An SNR of 84.3 dB in the 20 kHz audio band was achieved, when considering the noise from the 1st integrator and the quantizer.

Original language	English
Title of host publication	Proceedings of 32nd NORCHIP Conference
Number of pages	6
Publisher	IEEE
Publication date	2014
Article number	7004723
ISBN (Print)	978-1-4799-5441-4
DOIs	https://doi.org/10.1109/norchip.2014.7004723
Publication status	Published - 2014
Event	2014 IEEE 32nd NORCHIP Conference - Tampere, Finland Duration: 27 Oct 2014 → 28 Oct 2014 Conference number: 32 https://ieeexplore.ieee.org/xpl/conhome/6962987/proceeding

Conference

Conference	2014 IEEE 32nd NORCHIP Conference
Number	32
Country/Territory	Finland
City	Tampere
Period	27/10/2014 → 28/10/2014
Internet address	https://ieeexplore.ieee.org/xpl/conhome/6962987/proceeding

Keywords

Delta-Sigma ADC
Continuous-time
Circuit optimization
Circuit noise analysis

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10.1109/norchip.2014.7004723

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title = "Optimization of Modulator and Circuits for Low Power Continuous-Time Delta-Sigma ADC",

abstract = "This paper presents a new optimization method for achieving a minimum current consumption in a continuous-time Delta-Sigma analog-to-digital converter (ADC). The method is applied to a continuous-time modulator realised with active-RC integrators and with a folded-cascode operational transconduc- tance amplifier (OTA). Based on a detailed circuit analysis of the integrator and the OTA, key expression are derived relating the biasing current of the OTA to the noise requirements of the integrator. In the optimization the corner frequency of the modulator loop filter and the number of quantizer levels are swept. Based on the results of the circuit analysis, for each modulator combination the summed current consumption of the 1st integrator and quantizer of the ADC is determined. By also sweeping the partitioning of the noise power for the different circuit parts, the optimum modulator and circuit solution that fulfils a predefined set of performance requirements at minimum current is found. A design example is provided for a 3rd order modulator, achieving for the OTA of the 1st integrator and the quantizer a summed current consumption of 28 A. An SNR of 84.3 dB in the 20 kHz audio band was achieved, when considering the noise from the 1st integrator and the quantizer.",

keywords = "Delta-Sigma ADC, Continuous-time, Circuit optimization, Circuit noise analysis",

author = "Niels Marker-Villumsen and Erik Bruun",

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language = "English",

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booktitle = "Proceedings of 32nd NORCHIP Conference",

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note = "2014 IEEE 32nd NORCHIP Conference, NORCHIP 2014 ; Conference date: 27-10-2014 Through 28-10-2014",

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AU - Marker-Villumsen, Niels

AU - Bruun, Erik

N1 - Conference code: 32

PY - 2014

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N2 - This paper presents a new optimization method for achieving a minimum current consumption in a continuous-time Delta-Sigma analog-to-digital converter (ADC). The method is applied to a continuous-time modulator realised with active-RC integrators and with a folded-cascode operational transconduc- tance amplifier (OTA). Based on a detailed circuit analysis of the integrator and the OTA, key expression are derived relating the biasing current of the OTA to the noise requirements of the integrator. In the optimization the corner frequency of the modulator loop filter and the number of quantizer levels are swept. Based on the results of the circuit analysis, for each modulator combination the summed current consumption of the 1st integrator and quantizer of the ADC is determined. By also sweeping the partitioning of the noise power for the different circuit parts, the optimum modulator and circuit solution that fulfils a predefined set of performance requirements at minimum current is found. A design example is provided for a 3rd order modulator, achieving for the OTA of the 1st integrator and the quantizer a summed current consumption of 28 A. An SNR of 84.3 dB in the 20 kHz audio band was achieved, when considering the noise from the 1st integrator and the quantizer.

AB - This paper presents a new optimization method for achieving a minimum current consumption in a continuous-time Delta-Sigma analog-to-digital converter (ADC). The method is applied to a continuous-time modulator realised with active-RC integrators and with a folded-cascode operational transconduc- tance amplifier (OTA). Based on a detailed circuit analysis of the integrator and the OTA, key expression are derived relating the biasing current of the OTA to the noise requirements of the integrator. In the optimization the corner frequency of the modulator loop filter and the number of quantizer levels are swept. Based on the results of the circuit analysis, for each modulator combination the summed current consumption of the 1st integrator and quantizer of the ADC is determined. By also sweeping the partitioning of the noise power for the different circuit parts, the optimum modulator and circuit solution that fulfils a predefined set of performance requirements at minimum current is found. A design example is provided for a 3rd order modulator, achieving for the OTA of the 1st integrator and the quantizer a summed current consumption of 28 A. An SNR of 84.3 dB in the 20 kHz audio band was achieved, when considering the noise from the 1st integrator and the quantizer.

KW - Delta-Sigma ADC

KW - Continuous-time

KW - Circuit optimization

KW - Circuit noise analysis

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DO - 10.1109/norchip.2014.7004723

M3 - Article in proceedings

SN - 978-1-4799-5441-4

BT - Proceedings of 32nd NORCHIP Conference

PB - IEEE

T2 - 2014 IEEE 32nd NORCHIP Conference

Y2 - 27 October 2014 through 28 October 2014

ER -

Optimization of Modulator and Circuits for Low Power Continuous-Time Delta-Sigma ADC

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