One-way shared memory

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Abstract

Standard multicore processors use the shared main memory via the on-chip caches for communication between cores. However, this form of communication has two limitations: (1) it is hardly time-predictable and therefore not a good solution for real-time systems and (2) this single shared memory is a bottleneck in the system. This paper presents a communication architecture for time-predictable multicore systems where core-local memories are distributed on the chip. A network-on-chip constantly copies data from a sender core-local memory to a receiver core-local memory. As this copying is performed in one direction we call this architecture a one-way shared memory. With the use of time-division multiplexing for the memory accesses and the network-on-chip routers we achieve a time-predictable solution where the communication latency and bandwidth can be bounded. An example architecture for a 3×3 core processor and 32-bit wide links and memory ports provides a cumulative bandwidth of 29 bytes per clock cycle. Furthermore, the evaluation shows that this architecture, due to its simplicity, is small compared to other network-on-chip solutions.
Original languageEnglish
Title of host publicationProceedings of 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
PublisherIEEE
Publication date2018
Pages269-72
ISBN (Print)978-3-9819263-0-9
DOIs
Publication statusPublished - 2018
Event2018 Design, Automation & Test in Europe Conference & Exhibition - Internationales Congress Center, Dresden, Germany
Duration: 19 Mar 201823 Mar 2018

Conference

Conference2018 Design, Automation & Test in Europe Conference & Exhibition
LocationInternationales Congress Center
CountryGermany
CityDresden
Period19/03/201823/03/2018

Cite this

Schoeberl, M. (2018). One-way shared memory. In Proceedings of 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 269-72). IEEE. https://doi.org/10.23919/DATE.2018.8342017