On the Scalability of Time-predictable Chip-Multiprocessing

Real-time systems need a time-predictable execution platform to be able
to determine the worst-case execution time statically. In order to be
time-predictable, several advanced processor features, such as
out-of-order execution and other forms of speculation, have to be
avoided. However, just using simple processors is not an option for
embedded systems with high demands on computing power. In order to
provide high performance and predictability we argue to use
multiprocessor systems with a time-predictable memory interface. In this paper we present the scalability of a Java chip-multiprocessor system
that is designed to be time-predictable. Adding time-predictable caches
is mandatory to achieve scalability with a shared memory multi-processor system. As Java bytecode retains information about the nature of memory accesses, it is possible to implement a memory hierarchy that takes the characteristics of different types of accesses into account. For tasks 
with low communication the measured speedup of this time-predictable
system is in the range of 6 to 7 for eight processor cores, compared to
execution on a single-core processor.