Novel Clocking Scheme with Improved Voltage Gain for a Two-Phase Charge Pump Topology

Jakob Kenn Toft; Ivan Harald Holger Jørgensen

doi:10.1109/norchip.2019.8906942

Novel Clocking Scheme with Improved Voltage Gain for a Two-Phase Charge Pump Topology

Jakob Kenn Toft, Ivan Harald Holger Jørgensen

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

This paper presents a novel clocking scheme for the Favrat charge pump topology. The proposed clock scheme achieves an 8 % higher maximum power output and a 12 % higher maximum output voltage than the prior-art clock scheme. The novel clock scheme is part of the development of a very high voltage charge pump for MEMS applications. In this work a 46-stage charge pump based on the Favrat charge pump topology has been fabricated in a 180-nm SOI process with a > 200 V breakdown voltage. With an input voltage of 5 V the fabricated charge pump reach an output voltage of 185 V when driven by the proposed clock scheme and loaded with a 2 nA load, the prior-art clock scheme can only reach an output voltage of 165 V with a 2 nA load.

Original language	English
Title of host publication	Proceedings of 2019 IEEE Nordic Circuits and Systems Conference
Number of pages	7
Publisher	IEEE
Publication date	2019
Article number	8906942
ISBN (Print)	9781728127699
DOIs	https://doi.org/10.1109/norchip.2019.8906942
Publication status	Published - 2019
Event	2019 IEEE Nordic Circuits and Systems Conference - Helsinki, Finland Duration: 29 Oct 2019 → 30 Oct 2019 https://events.tuni.fi/norcas2019/

Conference

Conference	2019 IEEE Nordic Circuits and Systems Conference
Country	Finland
City	Helsinki
Period	29/10/2019 → 30/10/2019
Internet address	https://events.tuni.fi/norcas2019/

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10.1109/norchip.2019.8906942

FulltextAccepted author manuscript, 4.49 MB

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Cite this

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title = "Novel Clocking Scheme with Improved Voltage Gain for a Two-Phase Charge Pump Topology",

abstract = "This paper presents a novel clocking scheme for the Favrat charge pump topology. The proposed clock scheme achieves an 8 % higher maximum power output and a 12 % higher maximum output voltage than the prior-art clock scheme. The novel clock scheme is part of the development of a very high voltage charge pump for MEMS applications. In this work a 46-stage charge pump based on the Favrat charge pump topology has been fabricated in a 180-nm SOI process with a > 200 V breakdown voltage. With an input voltage of 5 V the fabricated charge pump reach an output voltage of 185 V when driven by the proposed clock scheme and loaded with a 2 nA load, the prior-art clock scheme can only reach an output voltage of 165 V with a 2 nA load.",

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year = "2019",

doi = "10.1109/norchip.2019.8906942",

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N2 - This paper presents a novel clocking scheme for the Favrat charge pump topology. The proposed clock scheme achieves an 8 % higher maximum power output and a 12 % higher maximum output voltage than the prior-art clock scheme. The novel clock scheme is part of the development of a very high voltage charge pump for MEMS applications. In this work a 46-stage charge pump based on the Favrat charge pump topology has been fabricated in a 180-nm SOI process with a > 200 V breakdown voltage. With an input voltage of 5 V the fabricated charge pump reach an output voltage of 185 V when driven by the proposed clock scheme and loaded with a 2 nA load, the prior-art clock scheme can only reach an output voltage of 165 V with a 2 nA load.

AB - This paper presents a novel clocking scheme for the Favrat charge pump topology. The proposed clock scheme achieves an 8 % higher maximum power output and a 12 % higher maximum output voltage than the prior-art clock scheme. The novel clock scheme is part of the development of a very high voltage charge pump for MEMS applications. In this work a 46-stage charge pump based on the Favrat charge pump topology has been fabricated in a 180-nm SOI process with a > 200 V breakdown voltage. With an input voltage of 5 V the fabricated charge pump reach an output voltage of 185 V when driven by the proposed clock scheme and loaded with a 2 nA load, the prior-art clock scheme can only reach an output voltage of 165 V with a 2 nA load.

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DO - 10.1109/norchip.2019.8906942

M3 - Article in proceedings

SN - 9781728127699

BT - Proceedings of 2019 IEEE Nordic Circuits and Systems Conference

PB - IEEE

T2 - 2019 IEEE Nordic Circuits and Systems Conference

Y2 - 29 October 2019 through 30 October 2019

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