Noise Properties of CMOS Current Conveyors

Erik Bruun

doi:10.1109/ISCAS.1996.539829

Noise Properties of CMOS Current Conveyors

Erik Bruun

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Abstract

The definition of the current conveyor is presented and it is shown how different generations of current conveyors can all be combined into a single definition of a multiple-output second generation current conveyor (CCII). Next, noise sources are introduced into the model, and a general noise model for the current conveyor is established. This model is used for the analysis of selected examples of current conveyor based operational amplifier configurations and the relative merits with respect to the noise performance of these configurations are discussed. Finally, the noise model is developed for a CMOS current conveyor implementation, and optimization strategies for noise reduction are discussed. It is concluded that a class AB implementation provides more flexibility than does a class A configuration. In both cases it is essential to design low noise current mirrors and current sources, and with the class AB design the current mirror and current source noise can be reduced by using small values of bias current without compromising the maximum available output current

Original language	English
Title of host publication	Proceedings of the 1996 IEEE International Symposium on Circuits and Systems
Volume	Volume 1
Publisher	IEEE
Publication date	1996
Pages	144-147
ISBN (Print)	0-7803-3073-0
DOIs	https://doi.org/10.1109/ISCAS.1996.539829
Publication status	Published - 1996
Event	1996 IEEE International Symposium on Circuits and Systems - Atlanta, GA, United States Duration: 12 May 1996 → 15 May 1996 http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=3834

Conference

Conference	1996 IEEE International Symposium on Circuits and Systems
Country/Territory	United States
City	Atlanta, GA
Period	12/05/1996 → 15/05/1996
Internet address	http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=3834

Bibliographical note

Copyright: 1996 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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title = "Noise Properties of CMOS Current Conveyors",

abstract = "The definition of the current conveyor is presented and it is shown how different generations of current conveyors can all be combined into a single definition of a multiple-output second generation current conveyor (CCII). Next, noise sources are introduced into the model, and a general noise model for the current conveyor is established. This model is used for the analysis of selected examples of current conveyor based operational amplifier configurations and the relative merits with respect to the noise performance of these configurations are discussed. Finally, the noise model is developed for a CMOS current conveyor implementation, and optimization strategies for noise reduction are discussed. It is concluded that a class AB implementation provides more flexibility than does a class A configuration. In both cases it is essential to design low noise current mirrors and current sources, and with the class AB design the current mirror and current source noise can be reduced by using small values of bias current without compromising the maximum available output current",

author = "Erik Bruun",

note = "Copyright: 1996 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE; 1996 IEEE International Symposium on Circuits and Systems, ISCAS'96 ; Conference date: 12-05-1996 Through 15-05-1996",

year = "1996",

doi = "10.1109/ISCAS.1996.539829",

language = "English",

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booktitle = "Proceedings of the 1996 IEEE International Symposium on Circuits and Systems",

publisher = "IEEE",

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TY - GEN

T1 - Noise Properties of CMOS Current Conveyors

AU - Bruun, Erik

N1 - Copyright: 1996 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

PY - 1996

Y1 - 1996

N2 - The definition of the current conveyor is presented and it is shown how different generations of current conveyors can all be combined into a single definition of a multiple-output second generation current conveyor (CCII). Next, noise sources are introduced into the model, and a general noise model for the current conveyor is established. This model is used for the analysis of selected examples of current conveyor based operational amplifier configurations and the relative merits with respect to the noise performance of these configurations are discussed. Finally, the noise model is developed for a CMOS current conveyor implementation, and optimization strategies for noise reduction are discussed. It is concluded that a class AB implementation provides more flexibility than does a class A configuration. In both cases it is essential to design low noise current mirrors and current sources, and with the class AB design the current mirror and current source noise can be reduced by using small values of bias current without compromising the maximum available output current

AB - The definition of the current conveyor is presented and it is shown how different generations of current conveyors can all be combined into a single definition of a multiple-output second generation current conveyor (CCII). Next, noise sources are introduced into the model, and a general noise model for the current conveyor is established. This model is used for the analysis of selected examples of current conveyor based operational amplifier configurations and the relative merits with respect to the noise performance of these configurations are discussed. Finally, the noise model is developed for a CMOS current conveyor implementation, and optimization strategies for noise reduction are discussed. It is concluded that a class AB implementation provides more flexibility than does a class A configuration. In both cases it is essential to design low noise current mirrors and current sources, and with the class AB design the current mirror and current source noise can be reduced by using small values of bias current without compromising the maximum available output current

U2 - 10.1109/ISCAS.1996.539829

DO - 10.1109/ISCAS.1996.539829

M3 - Article in proceedings

SN - 0-7803-3073-0

VL - Volume 1

SP - 144

EP - 147

BT - Proceedings of the 1996 IEEE International Symposium on Circuits and Systems

PB - IEEE

T2 - 1996 IEEE International Symposium on Circuits and Systems

Y2 - 12 May 1996 through 15 May 1996

ER -

Noise Properties of CMOS Current Conveyors

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