Noise Properties of CMOS Current Conveyors

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    The definition of the current conveyor is presented and it is shown how different generations of current conveyors can all be combined into a single definition of a multiple-output second generation current conveyor (CCII). Next, noise sources are introduced into the model, and a general noise model for the current conveyor is established. This model is used for the analysis of selected examples of current conveyor based operational amplifier configurations and the relative merits with respect to the noise performance of these configurations are discussed. Finally, the noise model is developed for a CMOS current conveyor implementation, and optimization strategies for noise reduction are discussed. It is concluded that a class AB implementation provides more flexibility than does a class A configuration. In both cases it is essential to design low noise current mirrors and current sources, and with the class AB design the current mirror and current source noise can be reduced by using small values of bias current without compromising the maximum available output current
    Original languageEnglish
    Title of host publicationProceedings of the 1996 IEEE International Symposium on Circuits and Systems
    VolumeVolume 1
    Publication date1996
    ISBN (Print)0-7803-3073-0
    Publication statusPublished - 1996
    Event1996 IEEE International Symposium on Circuits and Systems - Atlanta, GA, United States
    Duration: 12 May 199615 May 1996


    Conference1996 IEEE International Symposium on Circuits and Systems
    Country/TerritoryUnited States
    CityAtlanta, GA
    Internet address

    Bibliographical note

    Copyright: 1996 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE


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