Noise Analysis of Switched-Current Circuits

The understanding of noise in analog sampled data systems is vital for the design of high resolution circuitry in the discrete time domain. In this paper a general description of sampled and held noise is presened. The noise calculations are verified by measurements on an analog delay line implemented using switched-current (SI) technique. The SI delay line is based on a new topology current copier (CCOP). For the verification of the theory a new measurement technique is used. This technique enables one to measure the power spectral density of sampled and held noise which is below the continuous time noise floor.