Net Balanced Floorplanning Based on Elastic Energy Model

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    Abstract

    Floorplanning is becoming more and more important in VLSI design flows, especially for system-on-chip (SoC) designs where IP blocks dominate standard cells. Moreover, in deep sub-micron technologies, where process variations can introduce extra signal skew, it is desirable to have floorplans with balanced net delays to increase the safety margins of the design. In this paper, we investigate the properties of floorplanning based on the elastic energy model. The B*-tree, which is based on an ordered binary tree, is used for circuit representation and the elastic energy is used as the cost function. To evaluate how well a net is balanced, we introduced a new metric 'unbalancing'. A more balanced net would have a smaller 'unbalancing' value. Experimental results show that our approach can not only meet fixed-outline constraints, but also achieve significant improvements in net balance for all the circuits in the MCNC benchmark.
    Original languageEnglish
    Title of host publication2008 NORCHIP
    PublisherIEEE
    Publication date2008
    ISBN (Print)9781424424924
    DOIs
    Publication statusPublished - 2008
    Event2008 NORCHIP - Tallinn, Estonia
    Duration: 1 Jan 2008 → …

    Conference

    Conference2008 NORCHIP
    CityTallinn, Estonia
    Period01/01/2008 → …

    Bibliographical note

    Copyright: 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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