Floorplanning is becoming more and more important in VLSI design flows, especially for system-on-chip (SoC) designs where IP blocks dominate standard cells. Moreover, in deep sub-micron technologies, where process variations can introduce extra signal skew, it is desirable to have floorplans with balanced net delays to increase the safety margins of the design. In this paper, we investigate the properties of floorplanning based on the elastic energy model. The B*-tree, which is based on an ordered binary tree, is used for circuit representation and the elastic energy is used as the cost function. To evaluate how well a net is balanced, we introduced a new metric 'unbalancing'. A more balanced net would have a smaller 'unbalancing' value. Experimental results show that our approach can not only meet fixed-outline constraints, but also achieve significant improvements in net balance for all the circuits in the MCNC benchmark.
|Title of host publication||2008 NORCHIP|
|Publication status||Published - 2008|
|Event||2008 NORCHIP - Tallinn, Estonia|
Duration: 1 Jan 2008 → …
|Period||01/01/2008 → …|