Multi-rate Real Time Hybrid Simulation operated on a flexible LabVIEW real-time platform

Jacob Paamand Waldbjørn, Amin Maghareh, Ge Ou, Shirley J. Dyke, Henrik Stang*

*Corresponding author for this work

    Research output: Contribution to journalJournal articleResearchpeer-review

    Abstract

    This paper presents a real-time hybrid simulation (RTHS) strategy where the numerical and experimental substructures are executed at two different rates to optimize computational resources while maintaining an effective actuator control. The concept is referred to here as multi-rate real-time hybrid simulation (mrRTHS), and this approach is intended to enable low-cost RTHS by facilitating testing in the case of limited computational resources. Operated on a Laboratory Virtual Engineering Workshop (LabVIEW) real-time target, the mrRTHS concept is demonstrated through both a single- and multipledegree-of-freedom (SDOF) and (MDOF) mass-spring-damper system. The numerical substructure generates a displacement signal with a coarse time step of Δt. Using the current and three previous displacement data points, a finer control signal is defined with a time step of δt, using a third-order polynomial algorithm–referred to here as the polynomial fitting extrapolator. Both the numerical substructure and polynomial fitting extrapolator is executed with a sampling rate of Δt by an on-board single-core processor–referred to here as the digital signal processor (DSP). Through a field-programmable gate array (FPGA) the control signal is compensated and transmitted to the transfer system through an I/O module with a sampling rate of 1 kHz (i.e. δt = 0.001 sec). The ratio between Δt and δt are an integer–referred to here as the execution ratio. For an execution ratio of 1:5 and 1:10 the system performance is evaluated against a numerical model of the emulated structure–referred to here as the reference structure. For both the SDOF and MDOF system, a good correlation between the mrRTHS and reference is achieved with execution ratios of 1:5 and 1:10. When changing the execution ratio from 1:5 to 1:10, approximately 50% reduction of the required computational resources on the DSP is achieved.
    Original languageEnglish
    Article number112308
    JournalEngineering Structures
    Volume239
    ISSN0141-0296
    DOIs
    Publication statusPublished - 2021

    Keywords

    • Real-time hybrid simulation
    • Hardware-in-the-loop
    • Performance evaluation
    • Experimental substructure
    • Numerical substructure
    • Field programmable gate array

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