PCB layout for Gallium Nitride (GaN) transistor power loops are critical for achieving a stable operation in power converters. Optimal design should minimize the parasitic inductance as well as provide a low thermal resistance for heat dissipation. A multi-physic evaluation of performance between different PCB designs are made and a novel layout is proposed in this paper. The parasitic inductance and heat distribution of each layout are compared. The parasitic inductance is obtained from the oscillation frequency of the transistor drain-source voltage ringing. The thermal comparison is done with a combination of measurements and calculations. To ensure identical operating conditions, the buck converter adopts a modular design idea, where the plug-in totem poles of different designs are placed on the same motherboard. An optimized strategy for GaN transistor layout is given.
|Title of host publication||Proceedings of 34th annual IEEE Applied Power Electronics Conference and Exposition|
|Number of pages||7|
|Publication status||Published - 2019|
|Event||34th annual IEEE Applied Power Electronics Conference and Exposition - Anaheim convention center, Anaheim, United States|
Duration: 17 Mar 2019 → 21 Mar 2019
|Conference||34th annual IEEE Applied Power Electronics Conference and Exposition|
|Location||Anaheim convention center|
|Period||17/03/2019 → 21/03/2019|
- Gallium Nitride
- PCB layout
- Parasitic inductance
- Thermal analysis
- Multi-physic simulation
Sun, B., Jørgensen, K. L., Zhang, Z., & Andersen, M. A. E. (2019). Multi-physic Analysis for GaN Transistor PCB Layout. In Proceedings of 34th annual IEEE Applied Power Electronics Conference and Exposition IEEE.