Multi-physic Analysis for GaN Transistor PCB Layout

Bainan Sun, Kasper Lüthje Jørgensen, Zhe Zhang, Michael A. E. Andersen

    Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

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    Abstract

    PCB layout for Gallium Nitride (GaN) transistor power loops are critical for achieving a stable operation in power converters. Optimal design should minimize the parasitic inductance as well as provide a low thermal resistance for heat dissipation. A multi-physic evaluation of performance between different PCB designs are made and a novel layout is proposed in this paper. The parasitic inductance and heat distribution of each layout are compared. The parasitic inductance is obtained from the oscillation frequency of the transistor drain-source voltage ringing. The thermal comparison is done with a combination of measurements and calculations. To ensure identical operating conditions, the buck converter adopts a modular design idea, where the plug-in totem poles of different designs are placed on the same motherboard. An optimized strategy for GaN transistor layout is given.
    Original languageEnglish
    Title of host publicationProceedings of 34th annual IEEE Applied Power Electronics Conference and Exposition
    Number of pages7
    PublisherIEEE
    Publication date2019
    Publication statusPublished - 2019
    Event2019 IEEE Applied Power Electronics Conference and Exposition - Anaheim convention center, Anaheim, United States
    Duration: 17 Mar 201921 Mar 2019
    https://ieeexplore.ieee.org/xpl/conhome/8716496/proceeding

    Conference

    Conference2019 IEEE Applied Power Electronics Conference and Exposition
    LocationAnaheim convention center
    Country/TerritoryUnited States
    CityAnaheim
    Period17/03/201921/03/2019
    Internet address

    Keywords

    • Gallium Nitride
    • PCB layout
    • Parasitic inductance
    • Thermal analysis
    • Multi-physic simulation

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