Multi-dimensional reconciliation encoder with quasi-cyclic LDPC codes on FPGA

M. Origlia*, N. Andriolli, L. Maggiani, P. Castoldi, M. Secondini, E. Forestieri, T. Rydberg, T. Gehring

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

Abstract

Information reconciliation (IR) is an integral part of classical data post-processing in quantum key distribution (QKD) and often constitutes a performance bottleneck. Due to the low signal-to-noise ratio, continuous-variable QKD systems require a IR scheme, such as multi-dimensional reconciliation (MDR), which is particularly computationally intensive.In this work we present the hardware architecture of an MDR encoder employing Quasi-Cyclic Low Density Parity Check (QC-LDPC) codes. We estimate the required number of flip-flops and the latency of its FPGA implementation. Finally, we investigate the computational bottlenecks and identify solutions to improve the scalability of the proposed implementation.

Original languageEnglish
Title of host publicationProceedings of the 23rd International Conference on Transparent Optical Networks (ICTON)
Number of pages4
PublisherIEEE Computer Society Press
Publication date2023
ISBN (Electronic)979-8-3503-0303-2
DOIs
Publication statusPublished - 2023
Event23rd International Conference on Transparent Optical Networks - Bucharest, Romania
Duration: 2 Jul 20236 Jul 2023
Conference number: 23

Conference

Conference23rd International Conference on Transparent Optical Networks
Number23
Country/TerritoryRomania
CityBucharest
Period02/07/202306/07/2023

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