Multi-ASIP Platform Synthesis for Real-Time Applications

Laura Micconi, Deepak Gangadharan, Paul Pop, Jan Madsen

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review


In this paper we are interested in deriving a distributed platform, composed of heterogeneous processing elements, targeted to applications that have strict timing constraints. We consider that the platform may use multiple Application Specific Instruction Set Processors (ASIPs). An ASIP is synthesized and tuned for a specific set of tasks (i.e., a task cluster). During design space exploration (DSE), we evaluate each platform solution visited in terms of its cost and performance, i.e., its ability to execute the applications such that they meet their timing constraints. To determine if the applications are schedulable, we have to know the worst-case execution time (WCET) of each task. However, we can determine the WCETs only after the ASIPs are synthesized, which is time consuming and therefore cannot be done during DSE. To address this circular dependency (the ASIPs depend on the task clustering, and the WCETs of tasks, used to determine schedulability, depend on how ASIPs are synthesized), we propose an uncertainty model for the WCETs, which captures the range of possible ASIP implementations. Based on this model, we synthesize a multi-ASIP platform, such that the applications have a high chance of being schedulable and the cost constraints imposed on the platform are fulfilled. We propose an Evolutionary Algorithm-based approach, which uses a novel stochastic schedulability analysis to solve this optimization problem. The proposed approach has been evaluated using several benchmarks.
Original languageEnglish
Title of host publication2013 8th IEEE International Symposium on Industrial Embedded Systems (SIES)
Publication date2013
ISBN (Print)978-1-4799-0658-1
Publication statusPublished - 2013
Event8th IEEE International Symposium on Industrial Embedded Systems (SIES 2013) - Porto, Portugal
Duration: 19 Jun 201321 Jun 2013


Conference8th IEEE International Symposium on Industrial Embedded Systems (SIES 2013)
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