MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture

Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Berekovic

    Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review


    The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP) to applications by means of a sparsely interconnected array of functional units and register files. As high-ILP architectures achieve only low parallelism when executing partially sequential code segments, which is also known as Amdahl’s law, this paper proposes to extend ADRES to MT-ADRES (Multi-Threaded ADRES) to also exploit thread-level parallelism. On MT-ADRES architectures, the array can be partitioned in multiple smaller arrays that can execute threads in parallel. Because the partition can be changed dynamically, this extension provides more flexibility than a multi-core approach. This article presents details of the enhanced architecture and results obtained from an MPEG-2 decoder implementation that exploits a mix of thread-level parallelism and instruction-level parallelism.
    Original languageEnglish
    Title of host publicationReconfigurable Computing: Architectures, Tools and Applications : Lecture Notes in Computer Science
    PublisherSpringer Berlin / Heidelberg
    Publication date2007
    Publication statusPublished - 2007
    Event3rd International Workshop on Applied Reconfigurable Computing - Mangaratiba, Brazil
    Duration: 27 Mar 200729 Mar 2007
    Conference number: 3


    Workshop3rd International Workshop on Applied Reconfigurable Computing
    Internet address


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