Abstract
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP) to applications by means of a sparsely interconnected array of functional units and register files. As high-ILP architectures achieve only low parallelism when executing partially sequential code segments, which is also known as Amdahl’s law, this paper proposes to extend ADRES to MT-ADRES (Multi-Threaded ADRES) to also exploit thread-level parallelism. On MT-ADRES architectures, the array can be partitioned in multiple smaller arrays that can execute threads in parallel. Because the partition can be changed dynamically, this extension provides more flexibility than a multi-core approach. This article presents details of the enhanced architecture and results obtained from an MPEG-2 decoder implementation that exploits a mix of thread-level parallelism and instruction-level parallelism.
Original language | English |
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Title of host publication | Reconfigurable Computing: Architectures, Tools and Applications : Lecture Notes in Computer Science |
Volume | 4419/2007 |
Publisher | Springer Berlin / Heidelberg |
Publication date | 2007 |
Pages | 26-38 |
DOIs | |
Publication status | Published - 2007 |
Event | 3rd International Workshop on Applied Reconfigurable Computing - Mangaratiba, Brazil Duration: 27 Mar 2007 → 29 Mar 2007 Conference number: 3 http://www.informatik.uni-trier.de/~ley/db/conf/arc/arc2007.html |
Workshop
Workshop | 3rd International Workshop on Applied Reconfigurable Computing |
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Number | 3 |
Country/Territory | Brazil |
City | Mangaratiba |
Period | 27/03/2007 → 29/03/2007 |
Internet address |