Modular SoC-Design using the MANGO clockless NoC (Invited talk)

Tobias Bjerregaard (Invited author), Jens Sparsø (Invited author), Shankar Mahadevan (Invited author), Jan Madsen (Invited author)

    Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review


    Recent research has demonstrated the advantages of using shared, segmented interconnection networks for on-chip communication. Such on-chip networks (NoC) enable parallelism and counteract the physical effects of long wires. Network-on-Chip (NoC) thus facilitates a scalable design approach, while accommodating the advert effects technology scaling has on wire performance. Meanwhile, the demand for IP reuse and system level scalability in System-on-Chip (SoC) designs is growing. Managing the design flow of large complex chips presents a non-trivial challenge in its own right and NoC constitutes a viable solution space to emerging SoC design challenges. In MANGO (Message-passing Asynchronous Network-on-chip providing Guaranteed services over OCP interfaces) we address issues related to a modular and scalable system-on-chip (SoC) design flow. Key features of MANGO are (i) clockless implementation,implementation; (ii) standard socket access points based on OCP (Open Core Protocol) and (iii) guaranteed communication services. A clockless implementation promotes scalability by facilitating globally asynchronous locally synchronous (GALS) systems. GALS-type design makes the integration of cores with different timing characteristics an integral part of the design flow and reduces timing closure to a local problem. Standard sockets enables IP reuse and plug-and-play style system composition using IP cores from third party vendors. Connection-oriented latency and bandwidth guarantees promote predictability in system performance by reducing complex dynamic communication dependencies to static ones. This makes system analysis much easier, leading to advantages at all levels of SoC design. In this talk we present MANGO. We explain the basic architecture and argue how the above features are important, in exploiting the massive on-chip resources being made available by technology scaling. We explain how it fits into a system-level simulation framework, ARTS, which supports a modular SoC design and analysis flow bridging across the application, IP core, and NoC layers.
    Original languageEnglish
    Title of host publicationInternational Conference on Parallel Computing (PARCO'05)
    Place of PublicationPARCO
    Publication date2005
    Publication statusPublished - 2005
    EventInternational Conference on Parallel Computing - Malaga, Spain
    Duration: 13 Sept 200516 Sept 2005


    ConferenceInternational Conference on Parallel Computing

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