Models of Communication for Multicore Processors

Martin Schoeberl, Rasmus Bo Sørensen, Jens Sparsø

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

Abstract

To efficiently use multicore processors we need to ensure that almost all data communication stays on chip, i.e., the bits moved between tasks executing on different processor cores do not leave the chip. Different forms of on-chip communication are supported by different hardware mechanism, e.g., shared caches with cache coherency protocols, core-to-core networks-on-chip, and shared scratchpad memories. In this paper we explore the different hardware mechanism for on-chip communication and how they support or favor different models of communication. Furthermore, we discuss the usability of the different models of communication for real-time systems.
Original languageEnglish
Title of host publicationProceedings of the 18th IEEE International Symposium on Real-Time Distributed Computing (ISORC 2015)
PublisherIEEE Press
Publication date2015
Pages44-51
Publication statusPublished - 2015
Event18th IEEE International Symposium on Real-time Computing - Auckland, New Zealand
Duration: 13 Apr 201517 Apr 2015
Conference number: 18
http://www.isorc2015.org/

Conference

Conference18th IEEE International Symposium on Real-time Computing
Number18
CountryNew Zealand
CityAuckland
Period13/04/201517/04/2015
Internet address

Keywords

  • multicore communication
  • real-time systems
  • time- predictable systems

Cite this

Schoeberl, M., Sørensen, R. B., & Sparsø, J. (2015). Models of Communication for Multicore Processors. In Proceedings of the 18th IEEE International Symposium on Real-Time Distributed Computing (ISORC 2015) (pp. 44-51). IEEE Press.