Abstract
To efficiently use multicore processors we need to ensure that almost all data communication stays on chip, i.e., the bits moved between tasks executing on different processor cores do not leave the chip. Different forms of on-chip communication are supported by different hardware mechanism, e.g., shared caches with cache coherency protocols, core-to-core networks-on-chip, and shared scratchpad memories. In this paper we explore the different hardware mechanism for on-chip communication and how they support or favor different models of communication. Furthermore, we discuss the usability of the different models of communication for real-time systems.
| Original language | English |
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| Title of host publication | Proceedings of the 18th IEEE International Symposium on Real-Time Distributed Computing (ISORC 2015) |
| Publisher | IEEE Press |
| Publication date | 2015 |
| Pages | 44-51 |
| Publication status | Published - 2015 |
| Event | 18th IEEE International Symposium on Real-time Computing - Auckland, New Zealand Duration: 13 Apr 2015 → 17 Apr 2015 Conference number: 18 http://www.isorc2015.org/ |
Conference
| Conference | 18th IEEE International Symposium on Real-time Computing |
|---|---|
| Number | 18 |
| Country/Territory | New Zealand |
| City | Auckland |
| Period | 13/04/2015 → 17/04/2015 |
| Internet address |
Keywords
- multicore communication
- real-time systems
- time- predictable systems