A set of concurrent processes communicating through shared variables is an often used model for hardware systems. This paper presents three modeling techniques for representing such shared variables in VHDL, depending on the acceptable constraints on accesses to the variables. Also a set of guidelines for handling atomic updates of multiple shared variables is given. 1 Introduction It is often desirable to partition a computational system into discrete functional units which cooperates to.
|Title of host publication||Proceedings of the European Design Automation Conference with EURO-VHDL'94|
|Publication status||Published - 1994|
|Event||Proceedings of the European Design Automation Conference with EURO-VHDL'94 - |
Duration: 1 Jan 1994 → …
|Conference||Proceedings of the European Design Automation Conference with EURO-VHDL'94|
|Period||01/01/1994 → …|