Modeling Shared Variables in VHDL

Jan Madsen, Jens P. Brage

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    Abstract

    A set of concurrent processes communicating through shared variables is an often used model for hardware systems. This paper presents three modeling techniques for representing such shared variables in VHDL, depending on the acceptable constraints on accesses to the variables. Also a set of guidelines for handling atomic updates of multiple shared variables is given. 1 Introduction It is often desirable to partition a computational system into discrete functional units which cooperates to.
    Original languageEnglish
    Title of host publicationProceedings of the European Design Automation Conference with EURO-VHDL'94
    Publication date1994
    Publication statusPublished - 1994
    EventProceedings of the European Design Automation Conference with EURO-VHDL'94 -
    Duration: 1 Jan 1994 → …

    Conference

    ConferenceProceedings of the European Design Automation Conference with EURO-VHDL'94
    Period01/01/1994 → …

    Cite this

    Madsen, J., & Brage, J. P. (1994). Modeling Shared Variables in VHDL. In Proceedings of the European Design Automation Conference with EURO-VHDL'94