Modeling Shared Variables in VHDL

Jan Madsen; Jens P. Brage

Modeling Shared Variables in VHDL

Jan Madsen, Jens P. Brage

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

Abstract

A set of concurrent processes communicating through shared variables is an often used model for hardware systems. This paper presents three modeling techniques for representing such shared variables in VHDL, depending on the acceptable constraints on accesses to the variables. Also a set of guidelines for handling atomic updates of multiple shared variables is given. 1 Introduction It is often desirable to partition a computational system into discrete functional units which cooperates to.

Original language	English
Title of host publication	Proceedings of the European Design Automation Conference with EURO-VHDL'94
Publication date	1994
Publication status	Published - 1994
Event	European Design Automation Conference with EURO-VHDL'94 - Grenoble, France Duration: 19 Sept 1994 → 22 Sept 1994

Conference

Conference	European Design Automation Conference with EURO-VHDL'94
Country/Territory	France
City	Grenoble
Period	19/09/1994 → 22/09/1994

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title = "Modeling Shared Variables in VHDL",

abstract = "A set of concurrent processes communicating through shared variables is an often used model for hardware systems. This paper presents three modeling techniques for representing such shared variables in VHDL, depending on the acceptable constraints on accesses to the variables. Also a set of guidelines for handling atomic updates of multiple shared variables is given. 1 Introduction It is often desirable to partition a computational system into discrete functional units which cooperates to.",

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year = "1994",

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note = "European Design Automation Conference with EURO-VHDL'94 ; Conference date: 19-09-1994 Through 22-09-1994",

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AU - Brage, Jens P.

PY - 1994

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AB - A set of concurrent processes communicating through shared variables is an often used model for hardware systems. This paper presents three modeling techniques for representing such shared variables in VHDL, depending on the acceptable constraints on accesses to the variables. Also a set of guidelines for handling atomic updates of multiple shared variables is given. 1 Introduction It is often desirable to partition a computational system into discrete functional units which cooperates to.

M3 - Article in proceedings

BT - Proceedings of the European Design Automation Conference with EURO-VHDL'94

T2 - European Design Automation Conference with EURO-VHDL'94

Y2 - 19 September 1994 through 22 September 1994

ER -

Modeling Shared Variables in VHDL

Abstract

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