Abstract
In this work we present a hardware efficient matrix-vector multiplier architecture for artificial neural networks with digitally stored synapse strengths. We present a novel technique for manipulating bipolar inputs based on an analog two's complements method and an accurate current rectifier/sign detector. Measurements on a CMOS test chip are presented and validates the techniques. Further, we propose to use an analog extension, based on a simple capacitive storage, for enhancing weight resolution during learning. It is shown that the implementation of Hebbian learning and back-propagation learning in this system is possible using very little additional hardware compared to the recall mode system.
Original language | English |
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Journal | Analog Integrated Circuits and Signal Processing |
Volume | 9 |
Issue number | 1 |
Pages (from-to) | 55-63 |
ISSN | 0925-1030 |
DOIs | |
Publication status | Published - 1996 |