This paper addresses the design of self-timed energyminimum circuits, operating in the sub-VT domain. The paper presents a generic implementation template using bundled-data circuitry and current sensing completion detection. To support this, a fully-decoupled latch controller has been developed, which integrates the current sensing circuitry. The paper outlines a corresponding design flow, which is based on contemporary synchronous EDA tools, and which transforms a synchronous design, into a corresponding self-timed circuit. The design flow and the current-sensing technique is validated by the implementation of an asynchronous version of a wavelet based event detector for cardiac pacemaker applications in a standard 65nm CMOS process. The chip has been fabricated and the area overhead due to power domain separation and completion detection circuitry is 13.6 %. The improvement in throughput due to asynchronous operation is 52.58 %. By trading the throughput improvement, energy dissipation is reduced by 16.8% at the energy-minimum supply voltage.
|Title of host publication||Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'10)|
|Publisher||IEEE Computer Society Press|
|Publication status||Published - 2010|
|Event||16th IEEE International Symposium on Asynchronous Circuits and Systems - Grenoble, France|
Duration: 1 Jan 2010 → …
|Conference||16th IEEE International Symposium on Asynchronous Circuits and Systems|
|Period||01/01/2010 → …|