Measuring propagation losses of edge modes in photonic topological insulators

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Abstract

Photonic crystal structures in high-index materials such as silicon allow for subwavelength confinement of light [1] and enable engineering of compact devices for integrated photonics, as well as enhanced light-matter interaction by way of slow-light waveguides [2]. However, structural disorder [3] inherent to device fabrication induces backscattering and Anderson localization [4] and this is a major impediment to applications of photonic crystal waveguides.Topological insulators, first studied in the context of condensed matter, are materials that act as insulators in bulk while supporting propagating states along the edge. Notably, edge modes between materials with differing topological phases enjoy topological protection against backscattering. Photonic topological insulators (PTIs) [5, 6] are crystal structures engineered based on topological principles with the goal of supporting propagating edge states. In this way PTIs may offer a solution to the longstanding problem of backscattering in waveguides based on periodic structures. While robustness against artificially introduced defects on a scale of several unit cells has been demonstrated [7] protection against realistic fabrication disorder on the nanometer scale remains a topic of active theoretical research [8, 9].It is therefore of great practical relevance for the understanding and application of PTIs to also experimentally characterize the propagation losses for waveguides based on topological principles, especially so in devices exhibiting slow-light propagation. We have fabricated a series of valley-Hall PTIs from designs first proposed and experimentally demonstrated by Shalaev et al. [7] as well as interfaces modified to support slow-light propagation [10]. Fabricated structures are shown in Fig. 1. The devices are fabricated using commercial silicon-on-insulator (SOI) with a device layer thickness of 220 nm. The patterns are defined using 100 keV e-beam lithography and transferred into silicon using reactive-ion etching. The buried oxide layer is selectively removed using a vapor-phase hydrofluoric acid etch, producing out-of-plane-symmetric suspended silicon structures.To realistically benchmark PTI waveguide performance against established designs exhibiting a manifestly identical degree of roughness, they are fabricated next to conventional W1 waveguides of comparable parameters. We will report on the currently ongoing optical characterization where we use transmission measurements to study the propagation losses in the fabricated structures.
Original languageEnglish
Publication date2022
Number of pages2
Publication statusPublished - 2022
Event47th Micro and Nano Engineering Conference 2021 - Lingotto, Turin, Italy
Duration: 20 Sept 202123 Sept 2021
Conference number: 47
https://www.mne2021.org/

Conference

Conference47th Micro and Nano Engineering Conference 2021
Number47
LocationLingotto
Country/TerritoryItaly
CityTurin
Period20/09/202123/09/2021
Internet address

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