Mapping TSN Traffic Scheduling and Shaping to FPGA-based Architecture

Zifan Zhou, Michael Stübert Berger, Ying Yan

Research output: Contribution to journalJournal articlepeer-review

18 Downloads (Pure)

Abstract

Time-Sensitive Networking (TSN), which evolves from the Ethernet standards, has been developed to ensure deterministic transmission in data networks. Asynchronous Traffic Shaping (ATS) extends the conventional synchronized TSN with an asynchronous scheduler to guarantee a bounded transmitting delay. In this work, we present a Field Programmable Gate Arrays (FPGA) implementation of a TSN scheduling entity, which leverages ATS for the frame forwarding process. We explore the ATS design by function blocks and compare it with a benchmark design utilizing strict-priority scheduling. In terms of operating frequency, our results indicate that strict-priority scheduling performs 1.05% to 9.56% higher maximum frequency than ATS with the same configurations. Regarding resource utilization, ATS consumes 51% to 119% more logic blocks and 51% to 101% more registers than strict-priority scheduling. Based on the synthesis and fitting results from Register-Transfer Level (RTL) simulations, we provide a general vision of designing and implementing considerations of the ATS function. Specifically, we show the influences of the buffer and bus width configuration on the FPGA implementation scale and data rate.
Original languageEnglish
JournalIEEE Access
Volume8
Pages (from-to)221503-221512
ISSN2169-3536
DOIs
Publication statusPublished - 2020

Keywords

  • Ethernet networks
  • Real-time systems
  • Hardware
  • Scheduling algorithms
  • FPGA

Fingerprint

Dive into the research topics of 'Mapping TSN Traffic Scheduling and Shaping to FPGA-based Architecture'. Together they form a unique fingerprint.

Cite this