Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems

Viacheslav Izosimov; Paul Pop; Petru Eles; Zebo Peng

doi:10.1109/DSD.2006.65

Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems

Viacheslav Izosimov
, Paul Pop
, Petru Eles
, Zebo Peng

Linköping University

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

In this paper we present an approach for the mapping optimization of fault-tolerant embedded systems for safety-critical applications. Processes and messages are statically scheduled. Process re-execution is used for recovering from multiple transient faults. We call process recovery transparent if it does not affect operation of other processes. Transparent recovery has the advantage of fault containment, improved debugability and less memory needed to store the fault-tolerant schedules. However, it will introduce additional delays that can lead to violations of the timing constraints of the application. We propose an algorithm for the mapping of fault-tolerant applications with transparency. The algorithm decides a mapping of processes on computation nodes such that the application is schedulable and the transparency properties imposed by the designer are satisfied. The mapping algorithm is driven by a heuristic that is able to estimate the worst-case schedule length and indicate whether a certain mapping alternative is schedulable

Original language	English
Title of host publication	Euromicro Conference on Digital System Design
Place of Publication	Dubrovnik
Publication date	2006
Pages	312-322
ISBN (Print)	0-7695-2609-8
DOIs	https://doi.org/10.1109/DSD.2006.65
Publication status	Published - 2006
Event	9th Euromicro Conference on Digital System Design: Architectures, Methods and Tools - Dubrovnik, Croatia Duration: 30 Aug 2006 → 1 Sept 2006 Conference number: 9

Conference

Conference	9th Euromicro Conference on Digital System Design
Number	9
Country/Territory	Croatia
City	Dubrovnik
Period	30/08/2006 → 01/09/2006

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Copyright note for papers published by the IEEE Computer Society: Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works, must be obtained from the IEEE.

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title = "Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems",

abstract = "In this paper we present an approach for the mapping optimization of fault-tolerant embedded systems for safety-critical applications. Processes and messages are statically scheduled. Process re-execution is used for recovering from multiple transient faults. We call process recovery transparent if it does not affect operation of other processes. Transparent recovery has the advantage of fault containment, improved debugability and less memory needed to store the fault-tolerant schedules. However, it will introduce additional delays that can lead to violations of the timing constraints of the application. We propose an algorithm for the mapping of fault-tolerant applications with transparency. The algorithm decides a mapping of processes on computation nodes such that the application is schedulable and the transparency properties imposed by the designer are satisfied. The mapping algorithm is driven by a heuristic that is able to estimate the worst-case schedule length and indicate whether a certain mapping alternative is schedulable",

author = "Viacheslav Izosimov and Paul Pop and Petru Eles and Zebo Peng",

note = "Copyright note for papers published by the IEEE Computer Society: Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works, must be obtained from the IEEE.; 9th Euromicro Conference on Digital System Design : Architectures, Methods and Tools, DSD2006 ; Conference date: 30-08-2006 Through 01-09-2006",

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doi = "10.1109/DSD.2006.65",

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AU - Eles, Petru

AU - Peng, Zebo

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N2 - In this paper we present an approach for the mapping optimization of fault-tolerant embedded systems for safety-critical applications. Processes and messages are statically scheduled. Process re-execution is used for recovering from multiple transient faults. We call process recovery transparent if it does not affect operation of other processes. Transparent recovery has the advantage of fault containment, improved debugability and less memory needed to store the fault-tolerant schedules. However, it will introduce additional delays that can lead to violations of the timing constraints of the application. We propose an algorithm for the mapping of fault-tolerant applications with transparency. The algorithm decides a mapping of processes on computation nodes such that the application is schedulable and the transparency properties imposed by the designer are satisfied. The mapping algorithm is driven by a heuristic that is able to estimate the worst-case schedule length and indicate whether a certain mapping alternative is schedulable

AB - In this paper we present an approach for the mapping optimization of fault-tolerant embedded systems for safety-critical applications. Processes and messages are statically scheduled. Process re-execution is used for recovering from multiple transient faults. We call process recovery transparent if it does not affect operation of other processes. Transparent recovery has the advantage of fault containment, improved debugability and less memory needed to store the fault-tolerant schedules. However, it will introduce additional delays that can lead to violations of the timing constraints of the application. We propose an algorithm for the mapping of fault-tolerant applications with transparency. The algorithm decides a mapping of processes on computation nodes such that the application is schedulable and the transparency properties imposed by the designer are satisfied. The mapping algorithm is driven by a heuristic that is able to estimate the worst-case schedule length and indicate whether a certain mapping alternative is schedulable

U2 - 10.1109/DSD.2006.65

DO - 10.1109/DSD.2006.65

M3 - Article in proceedings

SN - 0-7695-2609-8

SP - 312

EP - 322

BT - Euromicro Conference on Digital System Design

CY - Dubrovnik

T2 - 9th Euromicro Conference on Digital System Design

Y2 - 30 August 2006 through 1 September 2006

ER -

Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems

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