M-PSK Demodulator with Joint Carrier and Timing Recovery

In this work, we propose a new digital receiver for Phase-Shift Keying (PSK) modulation based on the integration of the conventional digital Costas Loop circuit with a new timing recovery method. The timing recovery is applied to the PSK demodulator using an Iterative Learning Control (ILC) law and it is based on the minimization of the intersymbol interference using only one sample per symbol. The main advantage of the proposed timing recovery method is the insensitivity to frequency offsets which results in improved performance and robustness of the Costas Loop circuit. Experiments comparing a conventional receiver (cascade of Costas Loop and EarlyLate Timing Synchronizer) to the proposed receiver in scenarios characterized by low signal-to-noise ratios and large frequency and phase errors, show that the time needed to reduce the errors of the proposed receiver is seven times smaller than the conventional receiver. Moreover, the impact of the proposed method on the necessary hardware resources (area and power consumption) is negligible.