The aim of this work is the reduction of the power dissipated in digital filters, while maintaining the timing unchanged. A polyphase filter bank in the Quadratic Residue Number System (QRNS) has been implemented and then compared, in terms of performance, area, and power dissipation to the implementation of a polyphase filter bank in the traditional two's complement system (TCS). The resulting implementations, designed to have the same clock rates, show that the QRNS filter is smaller and consumes less power than the TCS one.
|Title of host publication||Proceedings of the 2004 International Symposium on Circuits and Systems, 2004 (ISCAS '04)|
|Publication status||Published - 2004|
|Event||2004 IEEE International Symposium on Circuits and Systems - Vancouver, Canada|
Duration: 23 May 2004 → 26 May 2004
|Conference||2004 IEEE International Symposium on Circuits and Systems|
|Period||23/05/2004 → 26/05/2004|