Low Capacitive Inductors for Fast Switching Devices in Active Power Factor Correction Applications

Juan Carlos Hernandez Botella, Lars Press Petersen, Michael A. E. Andersen

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Abstract

This paper examines different winding strategies for reduced capacitance inductors in active power factor correction circuits (PFC). The effect of the parasitic capacitance is analyzed from an electro magnetic compatibility (EMI) and efficiency point of views. The purpose of this work is to investigate different winding approaches and identify suitable solutions for high switching frequency/high speed transition PFC designs. A low parasitic capacitance PCB based inductor design is proposed to address the challenges imposed by high switching frequency PFC Boost converters.
Original languageEnglish
Title of host publicationProceedings of IPEC 2014
PublisherIEEE
Publication date2014
Pages3352-3357
ISBN (Print)9781479927050
DOIs
Publication statusPublished - 2014
EventIPEC 2014 : 2014 International Power Electronics Conference - Hiroshima, Japan
Duration: 18 May 201421 May 2014

Conference

ConferenceIPEC 2014
CountryJapan
CityHiroshima
Period18/05/201421/05/2014

Keywords

  • Parasitic capacitance
  • PFC
  • Boundry conduction mode (BCM)
  • High frequency

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