Low-area hardware implementations of CLOC, SILC and AES-OTR

Subhadeep Banik; Andrey Bogdanov; Kazuhiko Minematsu

doi:10.1109/HST.2016.7495559

Low-area hardware implementations of CLOC, SILC and AES-OTR

Subhadeep Banik
, Andrey Bogdanov
, Kazuhiko Minematsu

Department of Applied Mathematics and Computer Science

NEC Corporation

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

Abstract

The most compact implementation of the AES-128 algorithm was the 8-bit serial circuit proposed in the work of Moradi et. al. (Eurocrypt 2011). The circuit has an 8-bit datapath and occupies area equivalent to around 2400 GE. Since many authenticated encryption modes use the AES-128 algorithm as the underlying block cipher, we investigate if they can be implemented in a compact fashion using the 8-bit serialized AES circuit. In this context we investigate three authenticated encryption modes CLOC, SILC and AES-OTR. Using the standard cell library of the STM 90nm process, we implemented CLOC and SILC with around 3110 GE whereas AES-OTR was implemented with around 4720 GE.

Original language	English
Title of host publication	Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)
Publisher	IEEE
Publication date	2016
Pages	71-74
ISBN (Print)	978-1-4673-8825-2
DOIs	https://doi.org/10.1109/HST.2016.7495559
Publication status	Published - 2016
Event	2016 IEEE International Symposium on Hardware Oriented Security and Trust - The Ritz-Carlton, McLean, United States Duration: 3 May 2016 → 5 May 2016 https://ieeexplore.ieee.org/xpl/conhome/7489989/proceeding

Conference

Conference	2016 IEEE International Symposium on Hardware Oriented Security and Trust
Location	The Ritz-Carlton
Country/Territory	United States
City	McLean
Period	03/05/2016 → 05/05/2016
Internet address	https://ieeexplore.ieee.org/xpl/conhome/7489989/proceeding

Keywords

AES
Authenticated Encryption
CLOC
AES- OTR
SILC
Serialized Implementation

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@inproceedings{e7f470ebc6674ccfab5a9afb55b3a58a,

title = "Low-area hardware implementations of CLOC, SILC and AES-OTR",

abstract = "The most compact implementation of the AES-128 algorithm was the 8-bit serial circuit proposed in the work of Moradi et. al. (Eurocrypt 2011). The circuit has an 8-bit datapath and occupies area equivalent to around 2400 GE. Since many authenticated encryption modes use the AES-128 algorithm as the underlying block cipher, we investigate if they can be implemented in a compact fashion using the 8-bit serialized AES circuit. In this context we investigate three authenticated encryption modes CLOC, SILC and AES-OTR. Using the standard cell library of the STM 90nm process, we implemented CLOC and SILC with around 3110 GE whereas AES-OTR was implemented with around 4720 GE.",

keywords = "AES, Authenticated Encryption, CLOC, AES- OTR, SILC, Serialized Implementation",

author = "Subhadeep Banik and Andrey Bogdanov and Kazuhiko Minematsu",

year = "2016",

doi = "10.1109/HST.2016.7495559",

language = "English",

isbn = "978-1-4673-8825-2",

pages = "71--74",

booktitle = "Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)",

publisher = "IEEE",

address = "United States",

note = "2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016 ; Conference date: 03-05-2016 Through 05-05-2016",

url = "https://ieeexplore.ieee.org/xpl/conhome/7489989/proceeding",

}

Banik, S, Bogdanov, A & Minematsu, K 2016, Low-area hardware implementations of CLOC, SILC and AES-OTR. in Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST). IEEE, pp. 71-74, 2016 IEEE International Symposium on Hardware Oriented Security and Trust, McLean, Virginia, United States, 03/05/2016. https://doi.org/10.1109/HST.2016.7495559

TY - GEN

T1 - Low-area hardware implementations of CLOC, SILC and AES-OTR

AU - Banik, Subhadeep

AU - Bogdanov, Andrey

AU - Minematsu, Kazuhiko

PY - 2016

Y1 - 2016

N2 - The most compact implementation of the AES-128 algorithm was the 8-bit serial circuit proposed in the work of Moradi et. al. (Eurocrypt 2011). The circuit has an 8-bit datapath and occupies area equivalent to around 2400 GE. Since many authenticated encryption modes use the AES-128 algorithm as the underlying block cipher, we investigate if they can be implemented in a compact fashion using the 8-bit serialized AES circuit. In this context we investigate three authenticated encryption modes CLOC, SILC and AES-OTR. Using the standard cell library of the STM 90nm process, we implemented CLOC and SILC with around 3110 GE whereas AES-OTR was implemented with around 4720 GE.

AB - The most compact implementation of the AES-128 algorithm was the 8-bit serial circuit proposed in the work of Moradi et. al. (Eurocrypt 2011). The circuit has an 8-bit datapath and occupies area equivalent to around 2400 GE. Since many authenticated encryption modes use the AES-128 algorithm as the underlying block cipher, we investigate if they can be implemented in a compact fashion using the 8-bit serialized AES circuit. In this context we investigate three authenticated encryption modes CLOC, SILC and AES-OTR. Using the standard cell library of the STM 90nm process, we implemented CLOC and SILC with around 3110 GE whereas AES-OTR was implemented with around 4720 GE.

KW - AES

KW - Authenticated Encryption

KW - CLOC

KW - AES- OTR

KW - SILC

KW - Serialized Implementation

U2 - 10.1109/HST.2016.7495559

DO - 10.1109/HST.2016.7495559

M3 - Article in proceedings

SN - 978-1-4673-8825-2

SP - 71

EP - 74

BT - Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)

PB - IEEE

T2 - 2016 IEEE International Symposium on Hardware Oriented Security and Trust

Y2 - 3 May 2016 through 5 May 2016

ER -

Low-area hardware implementations of CLOC, SILC and AES-OTR

Abstract

Conference

Keywords

Access to Document

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