Low-area hardware implementations of CLOC, SILC and AES-OTR

Subhadeep Banik, Andrey Bogdanov, Kazuhiko Minematsu

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

Abstract

The most compact implementation of the AES-128 algorithm was the 8-bit serial circuit proposed in the work of Moradi et. al. (Eurocrypt 2011). The circuit has an 8-bit datapath and occupies area equivalent to around 2400 GE. Since many authenticated encryption modes use the AES-128 algorithm as the underlying block cipher, we investigate if they can be implemented in a compact fashion using the 8-bit serialized AES circuit. In this context we investigate three authenticated encryption modes CLOC, SILC and AES-OTR. Using the standard cell library of the STM 90nm process, we implemented CLOC and SILC with around 3110 GE whereas AES-OTR was implemented with around 4720 GE.
Original languageEnglish
Title of host publicationProceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)
PublisherIEEE
Publication date2016
Pages71-74
ISBN (Print)978-1-4673-8825-2
DOIs
Publication statusPublished - 2016
EventIEEE International Symposium on Hardware Oriented Security and Trust (HOST) - The Ritz-Carlton, McLean, VA, United States
Duration: 3 May 20165 May 2016
http://www.engr.uconn.edu/HOST/

Conference

ConferenceIEEE International Symposium on Hardware Oriented Security and Trust (HOST)
LocationThe Ritz-Carlton
CountryUnited States
CityMcLean, VA
Period03/05/201605/05/2016
Internet address

Keywords

  • AES
  • Authenticated Encryption
  • CLOC
  • AES- OTR
  • SILC
  • Serialized Implementation

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