Leveraging Predicated Execution for Multimedia Processing

Dietmar Ebner, Florian Brandner, Andreas Krall

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

Abstract

Modern compression standards such as H.264, DivX, or VC-1 provide astonishing quality at the costs of steadily increasing processing requirements. Therefore, efficient solutions for mobile multimedia devices have to effectively leverage instruction level parallelism (LLP), which is often achieved by the deployment of EPIC (explicitly parallel instruction computing) architectures. A characteristical architectural feature to increase the available ILP in the presence of control flow is predicated execution. Compilers targeting those hardware platforms are responsible to carefully convert control flow into conditional/predicated instructions - a process called if-conversion. We describe an effective if-conversion algorithm for the CHILI - a novel hardware architecture specifically designed for digital video processing and mobile multimedia consumer electronic. Several architectural characteristics such as the lack of branch prediction units, large delay slots, and the provided predication model are significantly different from previous work, typically aiming mainstream architectures such as Intel Itanium. The algorithm has been implemented for an optimizing compiler based on LLVM. Experimental results using a cycle accurate simulator for the well known benchmark suite MiBench and several multimedia codecs show a speed improvement of about 18% on average. On the same programs, our compiler achieves a speedup of 21% in comparison to the existing code generator based on gcc.
Keyword: instruction sets,optimizing compiler,if-conversion process,mobile multimedia consumer electronics,mobile multimedia devices,mobile computing,optimising compilers,EPIC architectures,multimedia computing,scheduling,explicitly parallel instruction computing,data flow computing,compression standards,branch prediction units,multimedia processing,parallel architectures,video coding,control flow feature,digital video processing,predicated execution leveraging,VLIW processor,instruction level parallelism,CHILI hardware architecture
Original languageEnglish
Title of host publication2007 IEEE/ACM/IFIP WORKSHOP ON EMBEDDED SYSTEMS FOR REAL-TIME MULTIMEDIA
PublisherIEEE
Publication date2007
Pages85-90
ISBN (Print)978-1-42441-654-7
DOIs
Publication statusPublished - 2007
Externally publishedYes
EventIEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia -
Duration: 1 Jan 2007 → …

Conference

ConferenceIEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia
Period01/01/2007 → …

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