Abstract
An accumulator instruction set architecture is simpler than an instruction set of a (reduced instruction set computer) RISC architecture. Therefore, an accumulator instruction set that does within one instruction less than a typical RISC instruction is probably more “reduced” than a standard load/store register based RISC architecture. This paper presents Leros, an accumulator machine and its supporting C compiler. The hypothesis of the Leros instruction set architecture is that it can deliver the same performance as a RISC pipeline, but consumes less hardware and therefore also less power.
Original language | English |
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Title of host publication | Architecture of Computing Systems - ARCS 2019 - 32nd International Conference, Proceedings |
Editors | Martin Schoeberl, Thilo Pionteck, Sascha Uhrig, Jürgen Brehm, Christian Hochberger |
Number of pages | 13 |
Publisher | Springer |
Publication date | 1 Jan 2019 |
Pages | 115-127 |
ISBN (Print) | 9783030186555 |
DOIs | |
Publication status | Published - 1 Jan 2019 |
Event | 32nd International Conference on Architecture of Computing Systems - Copenhagen, Denmark Duration: 20 May 2019 → 23 May 2019 Conference number: 32 |
Conference
Conference | 32nd International Conference on Architecture of Computing Systems |
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Number | 32 |
Country/Territory | Denmark |
City | Copenhagen |
Period | 20/05/2019 → 23/05/2019 |
Series | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
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Volume | 11479 LNCS |
ISSN | 0302-9743 |
Keywords
- Embedded systems
- Minimal processor