Abstract
An accumulator instruction set architecture is simpler than an instruction set of a (reduced instruction set computer) RISC architecture. Therefore, an accumulator instruction set that does within one instruction less than a typical RISC instruction is probably more “reduced” than a standard load/store register based RISC architecture. This paper presents Leros, an accumulator machine and its supporting C compiler. The hypothesis of the Leros instruction set architecture is that it can deliver the same performance as a RISC pipeline, but consumes less hardware and therefore also less power.
| Original language | English |
|---|---|
| Title of host publication | Architecture of Computing Systems - ARCS 2019 - 32nd International Conference, Proceedings |
| Editors | Martin Schoeberl, Thilo Pionteck, Sascha Uhrig, Jürgen Brehm, Christian Hochberger |
| Number of pages | 13 |
| Publisher | Springer |
| Publication date | 1 Jan 2019 |
| Pages | 115-127 |
| ISBN (Print) | 9783030186555 |
| DOIs | |
| Publication status | Published - 1 Jan 2019 |
| Event | 32nd International Conference on Architecture of Computing Systems, ARCS 2019 - Copenhagen, Denmark Duration: 20 May 2019 → 23 May 2019 |
Conference
| Conference | 32nd International Conference on Architecture of Computing Systems, ARCS 2019 |
|---|---|
| Country | Denmark |
| City | Copenhagen |
| Period | 20/05/2019 → 23/05/2019 |
| Series | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
|---|---|
| Volume | 11479 LNCS |
| ISSN | 0302-9743 |
Keywords
- Embedded systems
- Minimal processor
Cite this
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Leros : The return of the accumulator machine. / Schoeberl, Martin; Petersen, Morten Borup.
Architecture of Computing Systems - ARCS 2019 - 32nd International Conference, Proceedings. ed. / Martin Schoeberl; Thilo Pionteck; Sascha Uhrig; Jürgen Brehm; Christian Hochberger. Springer, 2019. p. 115-127 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 11479 LNCS).Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review
TY - GEN
T1 - Leros
T2 - The return of the accumulator machine
AU - Schoeberl, Martin
AU - Petersen, Morten Borup
PY - 2019/1/1
Y1 - 2019/1/1
N2 - An accumulator instruction set architecture is simpler than an instruction set of a (reduced instruction set computer) RISC architecture. Therefore, an accumulator instruction set that does within one instruction less than a typical RISC instruction is probably more “reduced” than a standard load/store register based RISC architecture. This paper presents Leros, an accumulator machine and its supporting C compiler. The hypothesis of the Leros instruction set architecture is that it can deliver the same performance as a RISC pipeline, but consumes less hardware and therefore also less power.
AB - An accumulator instruction set architecture is simpler than an instruction set of a (reduced instruction set computer) RISC architecture. Therefore, an accumulator instruction set that does within one instruction less than a typical RISC instruction is probably more “reduced” than a standard load/store register based RISC architecture. This paper presents Leros, an accumulator machine and its supporting C compiler. The hypothesis of the Leros instruction set architecture is that it can deliver the same performance as a RISC pipeline, but consumes less hardware and therefore also less power.
KW - Embedded systems
KW - Minimal processor
U2 - 10.1007/978-3-030-18656-2_9
DO - 10.1007/978-3-030-18656-2_9
M3 - Article in proceedings
SN - 9783030186555
SP - 115
EP - 127
BT - Architecture of Computing Systems - ARCS 2019 - 32nd International Conference, Proceedings
A2 - Schoeberl, Martin
A2 - Pionteck, Thilo
A2 - Uhrig, Sascha
A2 - Brehm, Jürgen
A2 - Hochberger, Christian
PB - Springer
ER -