Leros: A Tiny Microcontroller for FPGAs

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    Abstract

    Leros is a tiny microcontroller that is optimized for current low-cost FPGAs. Leros is designed with a balanced logic to on-chip memory relation. The design goal is a microcontroller that can be clocked in about half of the speed a pipelined on-chip memory and consuming less than 300 logic cells. The architecture, which follows from the design goals, is a pipelined 16-bit accumulator processor. An implementation of Leros needs at least one on-chip memory block and a few hundred logic cells. The application areas of Leros are twofold: First, it can be used as an intelligent peripheral device for auxiliary functions in an FPGA based system-on-chip design. Second, the very small size of Leros makes it an attractive soft core for many-core research with low-cost FPGAs.
    Original languageEnglish
    Title of host publicationProceedings of the 21st International Conference on Field Programmable Logic and Applications (FPL 2011)
    Publication date2011
    ISBN (Print)9781457714849
    DOIs
    Publication statusPublished - 2011
    Event21st International Conference on Field Programmable Logic and Applications (FPL 2011) -
    Duration: 1 Jan 2011 → …

    Conference

    Conference21st International Conference on Field Programmable Logic and Applications (FPL 2011)
    Period01/01/2011 → …

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