Leros: The return of the accumulator machine

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedings – Annual report year: 2019Researchpeer-review

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An accumulator instruction set architecture is simpler than an instruction set of a (reduced instruction set computer) RISC architecture. Therefore, an accumulator instruction set that does within one instruction less than a typical RISC instruction is probably more “reduced” than a standard load/store register based RISC architecture. This paper presents Leros, an accumulator machine and its supporting C compiler. The hypothesis of the Leros instruction set architecture is that it can deliver the same performance as a RISC pipeline, but consumes less hardware and therefore also less power.

Original languageEnglish
Title of host publicationArchitecture of Computing Systems - ARCS 2019 - 32nd International Conference, Proceedings
EditorsMartin Schoeberl, Thilo Pionteck, Sascha Uhrig, Jürgen Brehm, Christian Hochberger
Number of pages13
PublisherSpringer
Publication date1 Jan 2019
Pages115-127
ISBN (Print)9783030186555
DOIs
Publication statusPublished - 1 Jan 2019
Event32nd International Conference on Architecture of Computing Systems, ARCS 2019 - Copenhagen, Denmark
Duration: 20 May 201923 May 2019

Conference

Conference32nd International Conference on Architecture of Computing Systems, ARCS 2019
CountryDenmark
CityCopenhagen
Period20/05/201923/05/2019
SeriesLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume11479 LNCS
ISSN0302-9743
CitationsWeb of Science® Times Cited: No match on DOI

    Research areas

  • Embedded systems, Minimal processor

ID: 180157884