Layout Capacitive Coupling and Structure Impacts on Integrated High Voltage Power MOSFETs

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

106 Downloads (Pure)

Abstract

The switching performances of the integrated high voltage power MOSFETs that have prevailing interconnection matrices are being heavily influenced by the parasitic capacitive coupling of on-chip metal wires. The mechanism of the side-byside coupling is generally known, however, the layer-to-layer coupling and the comparison of the layout impacts have not been well established. This paper presents modeling of parasitic mutual coupling to analyze the parasitic capacitance directly coupled between two on-chip metal wires. The accurate 3D field solver analysis for the comparable dimensions shows that the layer-to-layer coupling can contribute higher impacts than the well-known side-by-side coupling. Four layout structures are then proposed and implemented in a 0.18 µm partial SOI process for 100 V integrated power MOSFETs with a die area 2.31 mm2. The post-layout comparison using an industrial 2D extraction tool shows that the side-by-side coupling dominated structure can perform better than the layer-to-layer coupling dominated structure, in terms of on-resistance times input or output capacitance, by 9.2% and 4.9%, respectively.
Original languageEnglish
Title of host publicationProceedings of IEEE 2016 12th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)
Number of pages4
PublisherIEEE
Publication date2016
ISBN (Print)978-1-5090-0493-5
Publication statusPublished - 2016
Event12th Conference on Ph.D Research in Microelectronics and Electronics (PRIME) - Lisbon, Portugal
Duration: 27 Jun 201630 Jun 2016

Conference

Conference12th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)
CountryPortugal
CityLisbon
Period27/06/201630/06/2016

Keywords

  • Integrated circuit interconnections
  • Layout
  • Mutual coupling
  • Parasitic capacitance
  • Power MOSFET

Cite this

Fan, L., Knott, A., & Jørgensen, I. H. H. (2016). Layout Capacitive Coupling and Structure Impacts on Integrated High Voltage Power MOSFETs. In Proceedings of IEEE 2016 12th Conference on Ph.D Research in Microelectronics and Electronics (PRIME) IEEE.
Fan, Lin ; Knott, Arnold ; Jørgensen, Ivan Harald Holger. / Layout Capacitive Coupling and Structure Impacts on Integrated High Voltage Power MOSFETs. Proceedings of IEEE 2016 12th Conference on Ph.D Research in Microelectronics and Electronics (PRIME). IEEE, 2016.
@inproceedings{c82f07dbda32460b95111977f637c741,
title = "Layout Capacitive Coupling and Structure Impacts on Integrated High Voltage Power MOSFETs",
abstract = "The switching performances of the integrated high voltage power MOSFETs that have prevailing interconnection matrices are being heavily influenced by the parasitic capacitive coupling of on-chip metal wires. The mechanism of the side-byside coupling is generally known, however, the layer-to-layer coupling and the comparison of the layout impacts have not been well established. This paper presents modeling of parasitic mutual coupling to analyze the parasitic capacitance directly coupled between two on-chip metal wires. The accurate 3D field solver analysis for the comparable dimensions shows that the layer-to-layer coupling can contribute higher impacts than the well-known side-by-side coupling. Four layout structures are then proposed and implemented in a 0.18 µm partial SOI process for 100 V integrated power MOSFETs with a die area 2.31 mm2. The post-layout comparison using an industrial 2D extraction tool shows that the side-by-side coupling dominated structure can perform better than the layer-to-layer coupling dominated structure, in terms of on-resistance times input or output capacitance, by 9.2{\%} and 4.9{\%}, respectively.",
keywords = "Integrated circuit interconnections, Layout, Mutual coupling, Parasitic capacitance, Power MOSFET",
author = "Lin Fan and Arnold Knott and J{\o}rgensen, {Ivan Harald Holger}",
year = "2016",
language = "English",
isbn = "978-1-5090-0493-5",
booktitle = "Proceedings of IEEE 2016 12th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)",
publisher = "IEEE",
address = "United States",

}

Fan, L, Knott, A & Jørgensen, IHH 2016, Layout Capacitive Coupling and Structure Impacts on Integrated High Voltage Power MOSFETs. in Proceedings of IEEE 2016 12th Conference on Ph.D Research in Microelectronics and Electronics (PRIME). IEEE, 12th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), Lisbon, Portugal, 27/06/2016.

Layout Capacitive Coupling and Structure Impacts on Integrated High Voltage Power MOSFETs. / Fan, Lin; Knott, Arnold; Jørgensen, Ivan Harald Holger.

Proceedings of IEEE 2016 12th Conference on Ph.D Research in Microelectronics and Electronics (PRIME). IEEE, 2016.

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

TY - GEN

T1 - Layout Capacitive Coupling and Structure Impacts on Integrated High Voltage Power MOSFETs

AU - Fan, Lin

AU - Knott, Arnold

AU - Jørgensen, Ivan Harald Holger

PY - 2016

Y1 - 2016

N2 - The switching performances of the integrated high voltage power MOSFETs that have prevailing interconnection matrices are being heavily influenced by the parasitic capacitive coupling of on-chip metal wires. The mechanism of the side-byside coupling is generally known, however, the layer-to-layer coupling and the comparison of the layout impacts have not been well established. This paper presents modeling of parasitic mutual coupling to analyze the parasitic capacitance directly coupled between two on-chip metal wires. The accurate 3D field solver analysis for the comparable dimensions shows that the layer-to-layer coupling can contribute higher impacts than the well-known side-by-side coupling. Four layout structures are then proposed and implemented in a 0.18 µm partial SOI process for 100 V integrated power MOSFETs with a die area 2.31 mm2. The post-layout comparison using an industrial 2D extraction tool shows that the side-by-side coupling dominated structure can perform better than the layer-to-layer coupling dominated structure, in terms of on-resistance times input or output capacitance, by 9.2% and 4.9%, respectively.

AB - The switching performances of the integrated high voltage power MOSFETs that have prevailing interconnection matrices are being heavily influenced by the parasitic capacitive coupling of on-chip metal wires. The mechanism of the side-byside coupling is generally known, however, the layer-to-layer coupling and the comparison of the layout impacts have not been well established. This paper presents modeling of parasitic mutual coupling to analyze the parasitic capacitance directly coupled between two on-chip metal wires. The accurate 3D field solver analysis for the comparable dimensions shows that the layer-to-layer coupling can contribute higher impacts than the well-known side-by-side coupling. Four layout structures are then proposed and implemented in a 0.18 µm partial SOI process for 100 V integrated power MOSFETs with a die area 2.31 mm2. The post-layout comparison using an industrial 2D extraction tool shows that the side-by-side coupling dominated structure can perform better than the layer-to-layer coupling dominated structure, in terms of on-resistance times input or output capacitance, by 9.2% and 4.9%, respectively.

KW - Integrated circuit interconnections

KW - Layout

KW - Mutual coupling

KW - Parasitic capacitance

KW - Power MOSFET

M3 - Article in proceedings

SN - 978-1-5090-0493-5

BT - Proceedings of IEEE 2016 12th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)

PB - IEEE

ER -

Fan L, Knott A, Jørgensen IHH. Layout Capacitive Coupling and Structure Impacts on Integrated High Voltage Power MOSFETs. In Proceedings of IEEE 2016 12th Conference on Ph.D Research in Microelectronics and Electronics (PRIME). IEEE. 2016