In this paper we explore the technique of "inverse gating" which is a significant improvement over the "round gating" technique introduced in HOST 2016. Round gating worked by generating timing signals to separate glitch propagation from one circuit element to the next. Inverse gating generates the same timing signals required to segregate transient round signals, in a manner that incurs less delay and hence lesser switching activity in the circuits. We also show that energy-wise, inverse gated circuits outperform round gated circuits by a margin of around 30 %. In the second part of the paper, we further explore the efficiency of the energy reduction by tuning some of the design parameters. The most natural candidate for this was the delay of the buffer used for creating the timing signals. We found that the optimal energy consumption for any round and inverse gated unrolled block cipher occurs at a particular range of this delay value. We try to explain the optimality of this particular choice of design parameter with the help of the implementation of the AES-128 block cipher.
|Title of host publication||Proceedings of 2018 Ieee International Symposium on Hardware Oriented Security and Trust (host).|
|Publication status||Published - 2018|
|Event||2018 Ieee International Symposium on Hardware Oriented Security and Trust - Hilton, Tysons Corner, McLean, United States|
Duration: 6 May 2018 → 10 May 2018
|Conference||2018 Ieee International Symposium on Hardware Oriented Security and Trust|
|Location||Hilton, Tysons Corner|
|Period||06/05/2018 → 10/05/2018|