Intrinsic Nonlinearities and Layout Impacts of 100 V Integrated Power MOSFETs in Partial SOI Process

Lin Fan; Arnold Knott; Ivan Harald Holger Jørgensen

Intrinsic Nonlinearities and Layout Impacts of 100 V Integrated Power MOSFETs in Partial SOI Process

Lin Fan, Arnold Knott, Ivan Harald Holger Jørgensen

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Abstract

Parasitic capacitances of power semiconductors are a part of the key design parameters of state-of-the-art very high frequency (VHF) power supplies. In this poster, four 100 V
integrated power MOSFETs with different layout structures are designed, implemented, and analyzed in a 0.18 ȝm partial Silicon-on-Insulator (SOI) process with a die area 2.31 mm². A small-signal model of power MOSFETs is proposed to systematically analyze the nonlinear parasitic capacitances in different transistor states: off-state, sub-threshold region, and on-state in the linear region. 3D plots are used to summarize the intrinsic nonlinearities of the power devices. The nonlinear figure-of-merits (FOMs) are lowered by 1.3-18.3 times and improved by 22-95 % with optimized conditions of quasi-zero voltage switching. The layout impacts of the on-chip interconnections are analyzed with post-layout comparisons.

Original language	English
Publication date	2016
Publication status	Published - 2016
Event	5th International Workshop on Power Supply On Chip - Centro de ELectronica Industrial, Madrid, Spain Duration: 3 Oct 2016 → 5 Oct 2016 Conference number: 5

Conference

Conference	5th International Workshop on Power Supply On Chip
Number	5
Location	Centro de ELectronica Industrial
Country/Territory	Spain
City	Madrid
Period	03/10/2016 → 05/10/2016

Bibliographical note

This e-poster has won the "Best Student E-poster Award" with a first prize issued by IEEE PELS (IEEE Power Electronics Society).

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title = "Intrinsic Nonlinearities and Layout Impacts of 100 V Integrated Power MOSFETs in Partial SOI Process",

abstract = "Parasitic capacitances of power semiconductors are a part of the key design parameters of state-of-the-art very high frequency (VHF) power supplies. In this poster, four 100 V integrated power MOSFETs with different layout structures are designed, implemented, and analyzed in a 0.18 ȝm partial Silicon-on-Insulator (SOI) process with a die area 2.31 mm2. A small-signal model of power MOSFETs is proposed to systematically analyze the nonlinear parasitic capacitances in different transistor states: off-state, sub-threshold region, and on-state in the linear region. 3D plots are used to summarize the intrinsic nonlinearities of the power devices. The nonlinear figure-of-merits (FOMs) are lowered by 1.3-18.3 times and improved by 22-95 \% with optimized conditions of quasi-zero voltage switching. The layout impacts of the on-chip interconnections are analyzed with post-layout comparisons.",

author = "Lin Fan and Arnold Knott and J{\o}rgensen, \{Ivan Harald Holger\}",

note = "This e-poster has won the {"}Best Student E-poster Award{"} with a first prize issued by IEEE PELS (IEEE Power Electronics Society).; 5th International Workshop on Power Supply On Chip, PwrSoC 2016 ; Conference date: 03-10-2016 Through 05-10-2016",

year = "2016",

language = "English",

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TY - CONF

T1 - Intrinsic Nonlinearities and Layout Impacts of 100 V Integrated Power MOSFETs in Partial SOI Process

AU - Fan, Lin

AU - Knott, Arnold

AU - Jørgensen, Ivan Harald Holger

N1 - Conference code: 5

PY - 2016

Y1 - 2016

N2 - Parasitic capacitances of power semiconductors are a part of the key design parameters of state-of-the-art very high frequency (VHF) power supplies. In this poster, four 100 V integrated power MOSFETs with different layout structures are designed, implemented, and analyzed in a 0.18 ȝm partial Silicon-on-Insulator (SOI) process with a die area 2.31 mm2. A small-signal model of power MOSFETs is proposed to systematically analyze the nonlinear parasitic capacitances in different transistor states: off-state, sub-threshold region, and on-state in the linear region. 3D plots are used to summarize the intrinsic nonlinearities of the power devices. The nonlinear figure-of-merits (FOMs) are lowered by 1.3-18.3 times and improved by 22-95 % with optimized conditions of quasi-zero voltage switching. The layout impacts of the on-chip interconnections are analyzed with post-layout comparisons.

AB - Parasitic capacitances of power semiconductors are a part of the key design parameters of state-of-the-art very high frequency (VHF) power supplies. In this poster, four 100 V integrated power MOSFETs with different layout structures are designed, implemented, and analyzed in a 0.18 ȝm partial Silicon-on-Insulator (SOI) process with a die area 2.31 mm2. A small-signal model of power MOSFETs is proposed to systematically analyze the nonlinear parasitic capacitances in different transistor states: off-state, sub-threshold region, and on-state in the linear region. 3D plots are used to summarize the intrinsic nonlinearities of the power devices. The nonlinear figure-of-merits (FOMs) are lowered by 1.3-18.3 times and improved by 22-95 % with optimized conditions of quasi-zero voltage switching. The layout impacts of the on-chip interconnections are analyzed with post-layout comparisons.

M3 - Poster

T2 - 5th International Workshop on Power Supply On Chip

Y2 - 3 October 2016 through 5 October 2016

ER -

Intrinsic Nonlinearities and Layout Impacts of 100 V Integrated Power MOSFETs in Partial SOI Process

Abstract

Conference

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