Intrinsic Nonlinearities and Layout Impacts of 100 V Integrated Power MOSFETs in Partial SOI Process

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Abstract

Parasitic capacitances of power semiconductors are a part of the key design parameters of state-of-the-art very high frequency (VHF) power supplies. In this poster, four 100 V
integrated power MOSFETs with different layout structures are designed, implemented, and analyzed in a 0.18 ȝm partial Silicon-on-Insulator (SOI) process with a die area 2.31 mm2.  A small-signal model of power MOSFETs is proposed to systematically analyze the nonlinear parasitic capacitances in different transistor states: off-state, sub-threshold region, and on-state in the linear region. 3D plots are used to summarize the intrinsic nonlinearities of the power devices. The nonlinear figure-of-merits (FOMs) are lowered by 1.3-18.3 times and improved by 22-95 % with optimized conditions of quasi-zero voltage switching. The layout impacts of the on-chip interconnections are analyzed with post-layout comparisons.
Original languageEnglish
Publication date2016
Publication statusPublished - 2016
Event 5th International Workshop on Power Supply On Chip - Centro de ELectronica Industrial, Madrid, Spain
Duration: 3 Oct 20165 Oct 2016
Conference number: 5

Conference

Conference 5th International Workshop on Power Supply On Chip
Number5
LocationCentro de ELectronica Industrial
CountrySpain
CityMadrid
Period03/10/201605/10/2016

Bibliographical note

This e-poster has won the "Best Student E-poster Award" with a first prize issued by IEEE PELS (IEEE Power Electronics Society).

Cite this

Fan, L., Knott, A., & Jørgensen, I. H. H. (2016). Intrinsic Nonlinearities and Layout Impacts of 100 V Integrated Power MOSFETs in Partial SOI Process. Poster session presented at 5th International Workshop on Power Supply On Chip, Madrid, Spain.