Interpolation by a prime factor other than 2 in low-voltage low-power ΣΔ DAC

Peter Pracný, Ivan Harald Holger Jørgensen, Liang Chen, Erik Bruun

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    Abstract

    This paper presents power optimization of a sigma-delta (ΣΔ) modulator based digital-to-analog converter (DAC) for hearing-aid audio back-end application. In a number of state-of-the-art publications the oversampling ratio (OSR) of the ΣΔ modulator is chosen as a factor of integer power of two. The reason given is the simplicity of the interpolation filter (IF) block. However, being able to choose OSR factors of integer powers of two only, might be restricting and not necessarily optimal. Therefore the ΣΔ modulator based DAC designs with multistage IF that include a stage performing oversampling by a factor of 3 are investigated. This new design freedom is used to lower the operating frequency of the whole DAC and save considerable amount of power. It is shown that the figure-of-merit (FOM) of such designs can be lower than designs using oversampling by a factor of integer powers of two. The same optimization approach can be used for other low voltage low power portable audio applications (mobile phones, notebook computers etc.).
    Original languageEnglish
    Title of host publicationProceedings of Norchip 2013
    Number of pages6
    PublisherIEEE
    Publication date2013
    ISBN (Print)978-1-4799-1647-4
    ISBN (Electronic)978-1-4799-1647-4
    DOIs
    Publication statusPublished - 2013
    Event2013 IEEE 31st NORCHIP Conference - Vilnius, Lithuania
    Duration: 11 Nov 201312 Nov 2013
    Conference number: 31
    https://ieeexplore.ieee.org/xpl/conhome/6693155/proceeding

    Conference

    Conference2013 IEEE 31st NORCHIP Conference
    Number31
    Country/TerritoryLithuania
    CityVilnius
    Period11/11/201312/11/2013
    Internet address

    Keywords

    • Sigma-delta modulator
    • Interpolation Filter
    • Class D
    • Hearing aid
    • Low voltage
    • Low Power

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