InterNoC: Unified Deterministic Communication For Distributed NoC-based Many-Core

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Abstract

Network-on-Chip is a popular paradigm for scalable many-core communication. There is a trend in modern system-on-chip to integrate more functionality. This combined with recent research for network-on-chip in the aerospace industry, gives room for design space exploration in new architectural paradigms for distributed and real-time many-core communication. In this paper, we present InterNoC, a deterministic communication scheme for distributed network-on-chip many-core that allows for unified IP-based timetriggered communication. It is hypothesized that such an architecture will efficiently minimize communication complexity in distributed many-core systems as well as provide hard-bounded endto-end latency guarantees. We extend the real-time multi-core platform T-CREST by introducing a time-triggered NoC-based switching mechanism combined with a NoC packet to Ethernet frame traffic controller. The proposed architecture will be evaluated in an experimental InterNoC network that implements a 36-core real-time system distributed over four FPGA devices.
Original languageEnglish
Title of host publicationProceedings of the 13th Junior Researcher Workshop on Real-Time Computing
Publication date2019
Pages29-32
Publication statusPublished - 2019
Event13th Junior Researcher Workshop on Real-Time Computing - Toulouse, France
Duration: 6 Nov 20198 Nov 2019
https://www.irit.fr/rtns2019/jrwrtc/

Conference

Conference13th Junior Researcher Workshop on Real-Time Computing
CountryFrance
CityToulouse
Period06/11/201908/11/2019
Internet address

Cite this

Kyriakakis, E., Sparsø, J., & Schoeberl, M. (2019). InterNoC: Unified Deterministic Communication For Distributed NoC-based Many-Core. In Proceedings of the 13th Junior Researcher Workshop on Real-Time Computing (pp. 29-32)