Abstract
This paper addresses the integration of stateless hardware accelerators into time-predictable multi-core platforms based on time-division multiplexing networks-on-chip. Stateless hardware accelerators, like floating-point units, are typically attached as co-processors to individual processors in the platform. Our design takes a different approach and connects the hardware accelerators to the network-on-chip in the same way as processor cores. Each processor that uses a hardware accelerator is assigned a virtual channel for sending instructions to the hardware accelerator and a virtual channel for receiving results. This allows a stateless and possibly pipelined hardware accelerator to be shared in an interleaved fashion without any form of reservation, and this opens for interesting area-performance trade-offs. The design is developed with a focus on time-predictability, areaefficiency, and FPGA implementation. The design evaluation is carried out using the open source T-CREST multi-core platform implemented on an Altera Cyclone IV FPGA. The size of the proposed design, including a floating-point accelerator, is about two-thirds of a processor.
Original language | English |
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Title of host publication | Proceedings of the 1st Nordic Circuits and Systems Conference (NORCAS 2015) |
Number of pages | 4 |
Publisher | IEEE |
Publication date | 2015 |
DOIs | |
Publication status | Published - 2015 |
Event | 2015 IEEE Nordic Circuits and Systems Conference - Oslo, Norway Duration: 26 Oct 2015 → 28 Oct 2015 Conference number: 1 https://ieeexplore.ieee.org/xpl/conhome/7360269/proceeding |
Conference
Conference | 2015 IEEE Nordic Circuits and Systems Conference |
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Number | 1 |
Country/Territory | Norway |
City | Oslo |
Period | 26/10/2015 → 28/10/2015 |
Other | A merge of NORCHIP and the International Symposium on System-on-Chip (SoC) |
Internet address |