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Abstract
This thesis reports on the analysis, design and implementation of E-band (71-86 GHz) power amplifiers in InP double heterojunction bipolar transistors (DHBTs) technology intended for next generation wireless communications systems. The wireless communication context and the typical requirements of power amplifiers are briefly discussed, pointing out the main limitations arising at such high frequencies. To extend the power capabilities of the InP DHBT technology, the possibility
of applying the stacked-transistor concept has been investigated in detail. A theoretical analysis based on the interstage matching between all the single transistors has been developed starting from the small-signal equivalent circuit. The analysis has been extended by including large-signal effects and layout-related limitations, which are thoroughly characterized by electromagnetic (EM) simulations. An evaluation of the maximum number of stacked transistors for positive incremental power and gain is also carried out. To validate the analysis, two-, three-, and four-stacked matched power cells have been realized as monolithic microwave integrated ciruits (MMICs) and tested for E-band operation. For instance, at 81 GHz, the two-stacked transistor power cell exhibits a small-signal gain of 6.4 dB, a measured maximum output power of 14.3 dBm and a peak power added efficiency (PAE) of 4.2 %. For the three-stacked transistor, a small-signal gain of 8.3 dB, a saturated output power of 15 dBm and a PAE of 5.2 % have been obtained at 81 GHz. At the same frequency, the four-stacked transistor achieves a small-signal gain of 11.5 dB, a saturated output power of 14.9 dBm and a peak PAE of 3.8 %. Various power amplifiers featuring parallel power combining have been designed as well. Good results are obtained from a four-way combined three-stacked configuration and from a two-stage eight-way combined power amplifier, which achieves an output power higher than 21.4 dBm at 75 GHz. The InP technology employed in this project is developed at III-V Lab (France) in two different processes. One is suited for high-speed mixed-signal applications and is denoted as SHARC process. The other, intended for power amplifiers, is denoted as SAND process. During the course of the project, III-V Lab’s clean rooms have been relocated in new premises in Palaiseau, leading to delays and difficulties in wafer fabrication. Albeit all circuits have been designed with SAND models, the functional fabricated wafers were in SHARC. Back-simulations, however, corroborated
simulations and experimental results.
of applying the stacked-transistor concept has been investigated in detail. A theoretical analysis based on the interstage matching between all the single transistors has been developed starting from the small-signal equivalent circuit. The analysis has been extended by including large-signal effects and layout-related limitations, which are thoroughly characterized by electromagnetic (EM) simulations. An evaluation of the maximum number of stacked transistors for positive incremental power and gain is also carried out. To validate the analysis, two-, three-, and four-stacked matched power cells have been realized as monolithic microwave integrated ciruits (MMICs) and tested for E-band operation. For instance, at 81 GHz, the two-stacked transistor power cell exhibits a small-signal gain of 6.4 dB, a measured maximum output power of 14.3 dBm and a peak power added efficiency (PAE) of 4.2 %. For the three-stacked transistor, a small-signal gain of 8.3 dB, a saturated output power of 15 dBm and a PAE of 5.2 % have been obtained at 81 GHz. At the same frequency, the four-stacked transistor achieves a small-signal gain of 11.5 dB, a saturated output power of 14.9 dBm and a peak PAE of 3.8 %. Various power amplifiers featuring parallel power combining have been designed as well. Good results are obtained from a four-way combined three-stacked configuration and from a two-stage eight-way combined power amplifier, which achieves an output power higher than 21.4 dBm at 75 GHz. The InP technology employed in this project is developed at III-V Lab (France) in two different processes. One is suited for high-speed mixed-signal applications and is denoted as SHARC process. The other, intended for power amplifiers, is denoted as SAND process. During the course of the project, III-V Lab’s clean rooms have been relocated in new premises in Palaiseau, leading to delays and difficulties in wafer fabrication. Albeit all circuits have been designed with SAND models, the functional fabricated wafers were in SHARC. Back-simulations, however, corroborated
simulations and experimental results.
Original language | English |
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Publisher | Technical University of Denmark |
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Number of pages | 132 |
Publication status | Published - 2018 |
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Dive into the research topics of 'InP DHBT MMIC Power Amplifiers for Millimeter-Wave Applications'. Together they form a unique fingerprint.Projects
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InP DHBT MMIC Power Amplifiers for Milimeter-Wave Applications
Squartecchia, M. (PhD Student), Johansen, T. K. (Main Supervisor), Dupuy, J.-Y. (Supervisor), Jakobsen, K. B. (Examiner), Colantonio, P. (Examiner) & Bao, M. (Examiner)
Marie Skłodowska-Curie actions
01/09/2014 → 07/11/2018
Project: PhD